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    1.
    发明专利
    未知

    公开(公告)号：DE69331341D1

    公开(公告)日：2002-01-24

    申请号：DE69331341

    申请日：1993-04-07

    Applicant: ALTERA CORP A DELAWARE CORP SA

    Inventor： CLIFF RICHARD G ,  LYTLE CRAIG SCHILLING ,  AHANIN BAHRAM ,  HEILE FRANCIS B ,  PEDERSEN BRUCE B ,  VEENSTRA KERRY

    IPC: H01L21/82 ,  H03K19/0175 ,  H03K19/173 ,  H03K19/177

    Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit.

    3.
    发明专利
    未知

    公开(公告)号：DE69223010D1

    公开(公告)日：1997-12-11

    申请号：DE69223010

    申请日：1992-08-06

    Applicant: ALTERA CORP

    Inventor： PEDERSON BRUCE B ,  CLIFF RICHARD G ,  AHANIN BAHRAM ,  LYTLE CRAIG SCHILLING ,  HEILE FRANCIS B ,  VEENSTRA KERRY SCOTT

    IPC: H01L21/82 ,  H03K19/173 ,  H03K19/177

    Abstract: A programmable logic array integrated circuit has a plurality of programmable logic elements grouped into a plurality of mutually exclusive groups. Each group includes signal conductors uniquely associated with that group for conveying signals between the programmable logic elements in that group. Other signal conductors are provided for conveying signals between the groups. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

    4.
    发明专利
    未知

    公开(公告)号：DE69928898D1

    公开(公告)日：2006-01-19

    申请号：DE69928898

    申请日：1999-10-25

    Applicant: ALTERA CORP

    Inventor： HEILE FRANCIS B

    IPC: G11C15/04 ,  G11C15/00

    Abstract: In order to eliminate or substantially eliminate the need for circuitry to encode the address outputs of a content addressable memory which is equipped to perform sum-of-products logic, the memory contents are stored in such a way that the sum-of-products circuitry can encode the address outputs. A data word may be stored at several different locations in the memory, each of those locations being associated with a respective one of the positions or places in the encoded address that is to contain an affirmative response when the stored data word matches an applied data word. The sum-of-products circuitry of the memory is used to logically combine the outputs of the memory associated with each place of the encoded address in order to produce the appropriately encoded address output signal for that place.

    5.
    发明专利
    未知

    公开(公告)号：DE69327670D1

    公开(公告)日：2000-02-24

    申请号：DE69327670

    申请日：1993-04-07

    Applicant: ALTERA CORP A DELAWARE CORP SA

    Inventor： CLIFF RICHARD G ,  LYTLE CRAIG SCHILLING ,  AHANIN BAHRAM ,  HEILE FRANCIS B ,  PEDERSEN BRUCE B ,  VEENSTRA KERRY

    IPC: H01L21/82 ,  H03K19/0175 ,  H03K19/173 ,  H03K19/177

    Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit.

    ASSOCIATIVE MEMORY ENCODING OUTPUT
    7.
    发明专利
    ASSOCIATIVE MEMORY ENCODING OUTPUT 失效

    公开(公告)号：JP2000149572A

    公开(公告)日：2000-05-30

    申请号：JP31443999

    申请日：1999-11-04

    Applicant: ALTERA CORP

    Inventor： HEILE FRANCIS B

    IPC: G11C15/04 ,  G11C15/00

    Abstract: PROBLEM TO BE SOLVED: To enable application of an associative memory capability by providing each aggregation of data word accumulation position in the memory correlated to each address output signal, accumulating each aggregation of each data word corresponding to each necessary address signal and forming a response to each data word within the aggregation and then generating an address output correlated to the aggregation. SOLUTION: Data word of a virtual address 1 is accumulated within the actual address position related to an output signal 110a and when the accumulated data word is adapted to the data word used through a conductor lead 205, only the output signal 110a is logical 1, gives a binary address 0001 and becomes the binary code of the virtual address 1. The data word of virtual address 6 is accumulated in the actual address position in relation to the output signals 110a, 110c. When the data word is adapted to the data word through a conductor 205, the output signals 110b, 110c become logical 1 to provide a binary address 0110.

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