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    PLD global communication network
    1.
    发明专利
    PLD global communication network 未知

    公开(公告)号：GB2284114A

    公开(公告)日：1995-05-24

    申请号：GB9419873

    申请日：1994-10-03

    Applicant: ALTERA CORP

    Inventor： VEENSTRA KERRY

    IPC: H03K19/173 ,  H03K19/177

    Abstract: Communication networks for integrated circuits such as programmable logic devices have a plurality of input conductors each of which is connected to two output multiplexers. For good signal routability through the network, no two multiplexers are connected to the same two input conductors. The girth of the multiplexer allocation graph associated with the network is four, and the graph is preferably a highly regular structure known as a cage or a regular structure derived from a cage. The input conductors are assigned to the edges in this regular graph in such a way that a highly regular pattern of connections between the input conductors and the multiplexers results to facilitate physical implementation of the network in the integrated circuit.

    TWO-TERMINAL MEMORY ARRAY WITH VARIABLE DEPTH AND WIDTH OF PROGRAMMABLE LOGIC ELEMENT
    2.
    发明专利
    TWO-TERMINAL MEMORY ARRAY WITH VARIABLE DEPTH AND WIDTH OF PROGRAMMABLE LOGIC ELEMENT 失效

    公开(公告)号：JPH11250667A

    公开(公告)日：1999-09-17

    申请号：JP29122198

    申请日：1998-10-13

    Applicant: ALTERA CORP

    Inventor： REDDY SRINIVAS T ,  LANE CHRISTOPHER F ,  MEJIA MANUEL ,  CLIFF RICHARD G ,  VEENSTRA KERRY

    IPC: G11C11/41 ,  G11C7/10

    Abstract: PROBLEM TO BE SOLVED: To write a data word into an array and at the same time read it from the array by independently operating a write row decoder, a data selection logic, and a write row address decoder and then a read row decoder, a data selection logic, and a read row address decoder. SOLUTION: A write address is transmitted to a write column address decoder 100, a write row decoder, and a data selection logic 106. A read address is transmitted to a read column address decoder 113, a read row decoder, and a data selection logic 120. On the other hand, an input multiplexer 100 independently transmits a write enable signal and a read permission signal to write enable 114 and read enable 140. A control logic 116 independently sets a secondary write enable means (WE) 118 and a secondary read enable means (RE) 142 to a higher level.

    PROGRAMMABLE LOGICAL ARCHITECTURE INCORPORATING CONTENT-ADDRESSABLE BURIED ARRAY BLOCK
    3.
    发明专利
    PROGRAMMABLE LOGICAL ARCHITECTURE INCORPORATING CONTENT-ADDRESSABLE BURIED ARRAY BLOCK 失效

    公开(公告)号：JPH11220382A

    公开(公告)日：1999-08-10

    申请号：JP31350798

    申请日：1998-11-04

    Applicant: ALTERA CORP

    Inventor： VEENSTRA KERRY ,  HEILE FRANCIS B

    IPC: G11C15/04 ,  H03K19/173

    Abstract: PROBLEM TO BE SOLVED: To obtain an efficient constitution by providing a multifunctional logic element capable of operating in plural logic modes according to a programming signal and a multifunctional memory element capable of operating in plural memory modes, one of which is a content addressable memory mode, according to the programming signal. SOLUTION: A true data line 228 and a complementary data line 230 are connected to an input driver 234 receiving a request word/data word B from an input line group 206. The driver 234 supplies a true data word signal and a complementary data word signal respectively for the lines 228 and 230. Selected one of true data lines 244 and selected one of complementary data lines 242 are programmably connected to an input line 240 to allow one of output drivers 284 to 294 selected through the use of a selecting signal received by an input driver 248 to form a desired output signal.

    5.
    发明专利
    未知

    公开(公告)号：DE69331341D1

    公开(公告)日：2002-01-24

    申请号：DE69331341

    申请日：1993-04-07

    Applicant: ALTERA CORP A DELAWARE CORP SA

    Inventor： CLIFF RICHARD G ,  LYTLE CRAIG SCHILLING ,  AHANIN BAHRAM ,  HEILE FRANCIS B ,  PEDERSEN BRUCE B ,  VEENSTRA KERRY

    IPC: H01L21/82 ,  H03K19/0175 ,  H03K19/173 ,  H03K19/177

    Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit.

    IMPROVED EMBEDDED LOGIC ANALYZER
    9.
    发明专利
    IMPROVED EMBEDDED LOGIC ANALYZER 失效

    公开(公告)号：JPH11296403A

    公开(公告)日：1999-10-29

    申请号：JP32792198

    申请日：1998-11-18

    Applicant: ALTERA CORP

    Inventor： VEENSTRA KERRY ,  RANGASAYEE KRISHNA ,  HERRMANN ALAN L

    IPC: G06F11/22 ,  G01R31/28 ,  G01R31/3177 ,  G01R31/3185 ,  G06F11/27 ,  G06F11/36 ,  G06F17/50 ,  H01L21/82 ,  H03K19/173

    Abstract: PROBLEM TO BE SOLVED: To provide a technique for embedding a logic analyzer for debug into a programmable logical device. SOLUTION: By embedding a logic analyzer into a programmable logic device(PLD) 16, it becomes possible to acquire a signal in both back and forth of a trigger condition (a break point). The logic analyzer embedding in the PLD 16 acquires and stores logic signals. In order to see on a computer, the logic analyzer unloads these signals. Using an electronic design automation(EDA) software tool which performs on the computer system, an engineer specifies a signal of the PLD of a monitoring object, the break point, the total number of samples of storage objects, the number of samples of an acquisition object after the break point is generated, and a system clock signal.

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