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    Programmable logic
    4.
    发明专利
    Programmable logic 未知

    公开(公告)号：GB2318198A

    公开(公告)日：1998-04-15

    申请号：GB9720542

    申请日：1997-09-26

    Applicant: ALTERA CORP

    Inventor： MCCLINTOCK CAMERON ,  NGO NINH D ,  CLIFF RICHARD G ,  ALTAF RISA

    IPC: H01L21/82 ,  H03K19/00 ,  H03K19/177

    Abstract: A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Each super-region may be like a small or moderately sized programmable logic device and may include a two-dimensional array of intersecting rows and columns of regions of programmable logic. Each region may in turn include a plurality of subregions of programmable logic. Horizontal and vertical inter-super-region interconnection conductors are associated with the rows and columns of super-regions. These conductors are selectively connectable to horizontal and vertical inter-region interconnection conductors in the super-regions.

    Soft error location and sensitivity detection for programmable devices
    5.
    发明专利
    Soft error location and sensitivity detection for programmable devices 有权
    可编程器件的软错误位置和灵敏度检测

    公开(公告)号：JP2007293856A

    公开(公告)日：2007-11-08

    申请号：JP2007112429

    申请日：2007-04-20

    Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

    Inventor： LEWIS DAVID ,  NGO NINH D ,  LEE ANDY L ,  HUANG JOSEPH

    IPC: G06F12/16 ,  G06F11/08 ,  G06F11/30 ,  H03K19/177

    CPC classification number: G11C29/52 ,  G06F11/1064 ,  H03K19/17764

    Abstract: PROBLEM TO BE SOLVED: To provide a method for detecting an error in a configuration memory of a programmable device. SOLUTION: The method for detecting errors in the configuration memory of the programmable device includes: reading configuration memory data from the configuration memory; determining whether an error occurs in the configuration memory data; reading sensitivity data corresponding to the configuration data being the error in response to determination that the error occurs; analyzing the sensitivity data in order to determine whether the error can be ignored; starting a remedial activity when the error can not be ignored; and ignoring the error by not starting the repair activity when the error can be ignored. COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种用于检测可编程设备的配置存储器中的错误的方法。 解决方案：用于检测可编程设备的配置存储器中的错误的方法包括：从配置存储器读取配置存储器数据; 确定配置存储器数据中是否发生错误; 响应于发生错误的确定，对应于作为错误的配置数据的读取敏感度数据; 分析灵敏度数据，以确定误差是否可以忽略; 当错误不能忽略时开始补救活动; 并且当错误可以忽略时，通过不启动修复活动来忽略该错误。 版权所有（C）2008，JPO＆INPIT

    Architectures for programmable logic devices
    6.
    发明专利
    Architectures for programmable logic devices 未知

    公开(公告)号：GB2318198B

    公开(公告)日：2000-10-25

    申请号：GB9720542

    申请日：1997-09-26

    Applicant: ALTERA CORP

    Inventor： MCCLINTOCK CAMERON ,  NGO NINH D ,  CLIFF RICHARD G ,  ALTAF RISA

    IPC: H01L21/82 ,  H03K19/00 ,  H03K19/177

    Abstract: A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Each super-region may be like a small or moderately sized programmable logic device and may include a two-dimensional array of intersecting rows and columns of regions of programmable logic. Each region may in turn include a plurality of subregions of programmable logic. Horizontal and vertical inter-super-region interconnection conductors are associated with the rows and columns of super-regions. These conductors are selectively connectable to horizontal and vertical inter-region interconnection conductors in the super-regions.

    Programmable logic array
    8.
    发明专利
    Programmable logic array 未知

    公开(公告)号：GB2312065A

    公开(公告)日：1997-10-15

    申请号：GB9706583

    申请日：1997-04-01

    Applicant: ALTERA CORP

    Inventor： LANE CHRISTOPHER F ,  LEE FUNG FUNG ,  MCCLINTOCK CAMERON ,  WANG BONNIE I ,  CLIFF RICHARD G ,  HEILE FRANCIS B ,  HUANG JOSEPH ,  MENDEL DAVID WOLK ,  NGO NINH D ,  PEDERSEN BRUCE B ,  REDDY SRINIVAS T ,  SUNG CHIAKANG ,  VEENSTRA KERRY

    IPC: H03K19/04 ,  H03K19/177

    Abstract: A programmable logic array integrated circuit device includes a plurality of regions of programmable logic 20 disposed in a two-dimensional array of intersecting rows and columns of such regions. Each row has a plurality of adjacent horizontal conductors 50, and each column has a plurality of adjacent vertical conductors 60. The regions 20 in a row are interspersed with groups of local conductors 40 which interconnect the adjacent regions (from both sides) and the associated horizontal and vertical conductors 50,60. The local conductors 40 can also be used for intra-region communication, as well as communication between adjacent regions 20. Secondary signals such as clocks and clears for the regions 20 can be drawn either from dedicated secondary signal conductors or normal region inputs. Memory cell requirements for region input signal selection are reduced by plural-stage progressively-finer selection.

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