公开(公告)号：JPH10334678A

公开(公告)日：1998-12-18

申请号：JP6997098

申请日：1998-03-19

Applicant: ALTERA CORP

Inventor： MADURAWE RAMINDA U ,  SMOLEN RICHARD G ,  LIANG MINCHANG ,  SANSBURY JAMES D ,  TURNER JOHN E ,  COSTELLO JOHN C ,  WONG MYRON W

IPC: G11C16/04 ,  G11C16/26 ,  G11C29/50 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide a biasing method of a dual low line EEPROM to reduce stress on the dielectric material window of cell. SOLUTION: A bias voltage is applied to the control gate 40 and floating gate 32 of the EEPROM cell 200 to result in a potential difference between the control gate voltage and floating gate voltage of about 0.5 V or less. A tunnel oxidization film area is remarkably reduced by biasing the control voltage and floating gate voltage of cell 200. Moreover, a write column voltage is selected on the basis of the control gate voltage to substantially keep the balance of the tunnel oxidization film area in all operation modes.