公开(公告)号：GB2304436B

公开(公告)日：2000-03-22

申请号：GB9617235

申请日：1996-08-16

Applicant: ALTERA CORP

Inventor： SANSBURY JAMES D ,  MADURAWE RAMINDA U

IPC: G11C16/04

Abstract: A memory cell (400) for storing data on an integrated circuit. The memory cell (400) is static, nonvolatile, and reprogrammable. The layout of the memory cell is compact. In a first state, the logic output from this memory cell (400) is at about voltage level at a first conductor (505); and in a second state, the logic output is at about a voltage level at a second conductor (510). The memory cell (400) of the present invention includes a first programmable memory element (515) and a second programmable memory element (520). First programmable memory element (515) is coupled between the first conductor (505) and a sensing node (405). Second programmable memory element (520) is coupled between the sensing node (405) and the second conductor (510). In the first state, first programmable memory element (515) is not programmed, while the second programmable memory element (520) is programmed. In the second state, first programmable memory element (515) is programmed, while second programmable memory element (520) is not programmed.

公开(公告)号：GB2312068A

公开(公告)日：1997-10-15

申请号：GB9707323

申请日：1997-04-10

Applicant: ALTERA CORP

Inventor： PASS CHRISTOPHER J ,  SANSBURY JAMES D ,  MADURAWE RAMINDA U ,  TURNER JOHN E ,  PATEL RAKESH H ,  WRIGHT PETER J

IPC: H03K19/177 ,  H03K19/0175

Abstract: A static, nonvolatile, and reprogrammable programmable interconnect junction cell for implementing programmable interconnect in an integrated circuit. The programmable interconnect junction (600) is programmably configured to couple or decouple a first interconnect line (210) and a second interconnect line (220). The configured state of the programmable interconnect junction is detected directly, and memory cell detection circuitry such as sense amplifiers are not needed during normal operation. Full-rail voltages may be passed from the first interconnect line and the second interconnect line. An interconnect transistor 610 and a memory transistor 635 share a floating gate 620 which is charged via a write transistor 650 and tunnel diode 660 and controlled from a line 670 via a capacitor 680. A read transistor 630 can be used for margin testing.

公开(公告)号：GB2312068B

公开(公告)日：2000-03-29

申请号：GB9707323

申请日：1997-04-10

Applicant: ALTERA CORP

Inventor： PASS CHRISTOPHER J ,  SANSBURY JAMES D ,  MADURAWE RAMINDA U ,  TURNER JOHN E ,  PATEL RAKESH H ,  WRIGHT PETER J

IPC: H03K19/177 ,  H03K19/0175

Abstract: A technique of fabricating a nonvolatile device includes forming a low doping region to aid in the reduction of substrate hot electrons. The nonvolatile device may be a floating gate device, such as a Flash, EEPROM, or EPROM memory cell. The low doping region has a lower doping concentration than that of the substrate. By reducing substrate hot electrons, this improves the reliability and longevity of the nonvolatile device.

公开(公告)号：GB2304436A

公开(公告)日：1997-03-19

申请号：GB9617235

申请日：1996-08-16

Applicant: ALTERA CORP

Inventor： SANSBURY JAMES D ,  MADURAWE RAMINDA U

IPC: G11C16/04

Abstract: A memory cell (400) for storing data on an integrated circuit. The memory cell (400) is static, nonvolatile, and reprogrammable. The layout of the memory cell is compact. In a first state, the logic output from this memory cell (400) is at about voltage level at a first conductor (505); and in a second state, the logic output is at about a voltage level at a second conductor (510). The memory cell (400) of the present invention includes a first programmable memory element (515) and a second programmable memory element (520). First programmable memory element (515) is coupled between the first conductor (505) and a sensing node (405). Second programmable memory element (520) is coupled between the sensing node (405) and the second conductor (510). In the first state, first programmable memory element (515) is not programmed, while the second programmable memory element (520) is programmed. In the second state, first programmable memory element (515) is programmed, while second programmable memory element (520) is not programmed.

公开(公告)号：JPH10334678A

公开(公告)日：1998-12-18

申请号：JP6997098

申请日：1998-03-19

Applicant: ALTERA CORP

Inventor： MADURAWE RAMINDA U ,  SMOLEN RICHARD G ,  LIANG MINCHANG ,  SANSBURY JAMES D ,  TURNER JOHN E ,  COSTELLO JOHN C ,  WONG MYRON W

IPC: G11C16/04 ,  G11C16/26 ,  G11C29/50 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide a biasing method of a dual low line EEPROM to reduce stress on the dielectric material window of cell. SOLUTION: A bias voltage is applied to the control gate 40 and floating gate 32 of the EEPROM cell 200 to result in a potential difference between the control gate voltage and floating gate voltage of about 0.5 V or less. A tunnel oxidization film area is remarkably reduced by biasing the control voltage and floating gate voltage of cell 200. Moreover, a write column voltage is selected on the basis of the control gate voltage to substantially keep the balance of the tunnel oxidization film area in all operation modes.