公开(公告)号：GB2287114B

公开(公告)日：1997-07-23

申请号：GB9502735

申请日：1995-02-13

Applicant: ALTERA CORP

Inventor： COSTELLO JOHN C ,  PATEL RAKESH H

IPC: H03K19/173 ,  H03K19/177

Abstract: A programmable logic device is provided that contains a plurality of logic array blocks arranged in rows and columns. The logic array blocks are interconnected with horizontal conductors in each row and vertical conductors in each column. The logic array blocks and the interconnections between conductors are configured using programmable logic. Some of the programmable logic is used to selectively connect logic array block input terminals to the horizontal conductors. Additional logic in each column is used to selectively connect the horizontal conductors to either logic array block output terminals from the same column or logic array block output terminals from an adjacent column. The additional logic prevents certain interconnection pathways from being blocked and increases the overall flexibility of the interconnection scheme of the programmable logic device, thereby improving device performance.

公开(公告)号：GB2287114A

公开(公告)日：1995-09-06

申请号：GB9502735

申请日：1995-02-13

Applicant: ALTERA CORP

Inventor： COSTELLO JOHN C ,  PATEL RAKESH H

IPC: H03K19/173 ,  H03K19/177

Abstract: A programmable logic device contains a plurality of logic array blocks 16 arranged in rows and columns. The logic array blocks are interconnected with horizontal conductors in each row and vertical conductors in each column. The logic array blocks and the interconnections between conductors are configured using programmable logic. Each block 16 is fed from horizontal conductors via multiplexers 20, and feeds horizontal conductors via multiplexers 28 and vertical conductors via demultiplexers 26. Multiplexers 28 are also fed from the blocks 16 in the next adjacent columns via conductors 36, 40.

公开(公告)号：JPH10334678A

公开(公告)日：1998-12-18

申请号：JP6997098

申请日：1998-03-19

Applicant: ALTERA CORP

Inventor： MADURAWE RAMINDA U ,  SMOLEN RICHARD G ,  LIANG MINCHANG ,  SANSBURY JAMES D ,  TURNER JOHN E ,  COSTELLO JOHN C ,  WONG MYRON W

IPC: G11C16/04 ,  G11C16/26 ,  G11C29/50 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide a biasing method of a dual low line EEPROM to reduce stress on the dielectric material window of cell. SOLUTION: A bias voltage is applied to the control gate 40 and floating gate 32 of the EEPROM cell 200 to result in a potential difference between the control gate voltage and floating gate voltage of about 0.5 V or less. A tunnel oxidization film area is remarkably reduced by biasing the control voltage and floating gate voltage of cell 200. Moreover, a write column voltage is selected on the basis of the control gate voltage to substantially keep the balance of the tunnel oxidization film area in all operation modes.