公开(公告)号：AU2011240803B2

公开(公告)日：2014-05-29

申请号：AU2011240803

申请日：2011-04-11

Applicant: APPLE INC

Inventor： HENDRY IAN ,  KODURI RAJABALI ,  GONION JEFFRY

IPC: G06F12/02 ,  G06F1/32 ,  G06F12/06

Abstract: [00134] Systems, methods, and devices for dynamically mapping and remapping memory when a portion of memory is activated or deactivated are provided. In accordance with an embodiment, an electronic device may include several memory banks, one or more processors, and a memory controller. The memory banks may store data in hardware memory locations and may be independently deactivated. The processors may request the data using physical memory addresses, and the memory controller may translate the physical addresses to hardware memory locations. The memory controller may use a first memory mapping function when a first number of memory banks is active and a second memory mapping function when a second number is active. When one of the memory banks is to be deactivated, the memory controller may copy data from only the memory bank that is to be deactivated to the active remainder of memory banks.

公开(公告)号：AU2022332113A1

公开(公告)日：2024-03-07

申请号：AU2022332113

申请日：2022-08-23

Applicant: APPLE INC

Inventor： HAMMARLUND PER ,  ZIMET LIOR ,  KOLOR SERGIO ,  LAHAV SAGI ,  VASH JAMES ,  GARG GAURAV ,  KUZI TAL ,  GONION JEFFRY ,  TUCKER CHARLES ,  LEVY-RUBIN LITAL ,  DAVIDOV DANY ,  FISHWICK STEVEN ,  LESHEM NIR ,  PILIP MARK ,  WILLIAMS III ,  KAUSHIKKAR HARSHAVARDHAN ,  SRIDHARAN SRINIVASA ,  TAMARI ERAN ,  TOTA SERGIO ,  REDSHAW JONATHAN ,  HUTSELL STEVEN ,  FUKAMI SHAWN ,  GUNNA RAMESH

IPC: G06F3/06 ,  G06F13/10 ,  G06F15/78

Abstract: A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture. An interconnect fabric included in the system includes at least two networks having heterogeneous interconnect topologies. The at least two networks include a coherent network interconnecting the processor cores and the plurality of memory controllers.

公开(公告)号：AU2011240803A1

公开(公告)日：2012-11-22

申请号：AU2011240803

申请日：2011-04-11

Applicant: APPLE INC

Inventor： HENDRY IAN ,  KODURI RAJABALI ,  GONION JEFFRY

IPC: G06F12/02 ,  G06F1/32 ,  G06F12/06

Abstract: [00134] Systems, methods, and devices for dynamically mapping and remapping memory when a portion of memory is activated or deactivated are provided. In accordance with an embodiment, an electronic device may include several memory banks, one or more processors, and a memory controller. The memory banks may store data in hardware memory locations and may be independently deactivated. The processors may request the data using physical memory addresses, and the memory controller may translate the physical addresses to hardware memory locations. The memory controller may use a first memory mapping function when a first number of memory banks is active and a second memory mapping function when a second number is active. When one of the memory banks is to be deactivated, the memory controller may copy data from only the memory bank that is to be deactivated to the active remainder of memory banks.