公开(公告)号：KR20180039645A

公开(公告)日：2018-04-18

申请号：KR20187005036

申请日：2016-06-20

Applicant: ADVANCED RISC MACH LTD ,  APPLE INC

Inventor： EYOLE MBOU ,  STEPHENS NIGEL JOHN ,  GONION JEFFREY ,  KLAIBER ALEX ,  TUCKER CHARLES

IPC: G06F15/80 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38

CPC classification number: G06F15/8076 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/30192 ,  G06F9/345 ,  G06F9/3455 ,  G06F9/355 ,  G06F9/3887

Abstract: 메모리와복수의벡터레지스터와의사이에서복수의데이터구조체를전송하는장치및 방법을제공하고, 각벡터레지스터는복수의데이터요소를포함하는벡터오퍼랜드를저장하도록배치된다. 액세스회로는, 메모리에있어서데이터구조체들과지정된벡터레지스터들과의사이에서벡터오퍼랜드들의데이터요소들을이동하는액세스연산들을행하는데사용되고, 각데이터구조는상기메모리에서인접어드레스들에저장된다수의데이터요소를포함한다. 디코드회로는, 상기메모리에서서로에대해비인접하게위치된복수의데이터구조체와복수의벡터레지스터를식별하는단일액세스명령어에응답하여, 각벡터레지스터에서의벡터오퍼랜드가상기복수의데이터구조체의각각으로부터대응한데이터요소를보유하도록, 상기액세스회로를제어하여상기메모리와상기복수의벡터레지스터와의사이에서상기복수의데이터구조체를이동하기위해서상기액세스연산들의시퀀스를행하기위한제어신호들을생성하는회로다. 이것은복잡한액세스연산들을행하기위한매우효율적인메카니즘을제공하여, 실행속도가증가하게되고, 소비전력이감소될가능성이있다.

公开(公告)号：AU2022332113A1

公开(公告)日：2024-03-07

申请号：AU2022332113

申请日：2022-08-23

Applicant: APPLE INC

Inventor： HAMMARLUND PER ,  ZIMET LIOR ,  KOLOR SERGIO ,  LAHAV SAGI ,  VASH JAMES ,  GARG GAURAV ,  KUZI TAL ,  GONION JEFFRY ,  TUCKER CHARLES ,  LEVY-RUBIN LITAL ,  DAVIDOV DANY ,  FISHWICK STEVEN ,  LESHEM NIR ,  PILIP MARK ,  WILLIAMS III ,  KAUSHIKKAR HARSHAVARDHAN ,  SRIDHARAN SRINIVASA ,  TAMARI ERAN ,  TOTA SERGIO ,  REDSHAW JONATHAN ,  HUTSELL STEVEN ,  FUKAMI SHAWN ,  GUNNA RAMESH

IPC: G06F3/06 ,  G06F13/10 ,  G06F15/78

Abstract: A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture. An interconnect fabric included in the system includes at least two networks having heterogeneous interconnect topologies. The at least two networks include a coherent network interconnecting the processor cores and the plurality of memory controllers.