Abstract:
A method of patterning of at least a layer in a semiconductor device, comprising a patterning step by patterning means wherein the patterned layer comprises sensing-light transmissive portions (702x) and sensing-light blocking portions (702).
Abstract:
Increasingly, metrology systems are integrated within the lithographic apparatuses, to provide integrated metrology within the lithographic process. However, this integration can result in a throughput or productivity impact of the whole lithographic apparatus which can be difficult to predict. It is therefore proposed to provide a simulation model which is operable to acquire throughput information associated with a throughput of a plurality of substrates within a lithographic apparatus, said throughput information comprising a throughput parameter, predict, using a throughput simulator the throughput using the throughput parameter as an input parameter. The throughput simulator may be calibrated using the acquired throughput information. The impact of at least one change of a throughput parameter on the throughput of the lithographic apparatus may be predicted using the throughput simulator.
Abstract:
Methods and apparatus for estimating at least part of a shape of a surface of a substrate usable in fabrication of semiconductor devices. Methods comprise: obtaining at least one focal position of the surface of the substrate measured by an inspection apparatus, the at least one focal position for bringing targets on or in the substrate within a focal range of optics of the inspection apparatus; and determining the at least part of the shape of the surface of the substrate based on the at least one focal position.
Abstract:
Described herein is a method for inspection of a patterning device. The method includes obtaining (i) patterning device apparatus data of a patterning device making process, (ii) a patterning device substrate map based on the patterning device apparatus data, and (iii) predicted process window limiting pattern locations corresponding to the patterning device based on the patterning device substrate map, and based on the process window limiting pattern locations, guiding, by a hardware computer system, a patterning device inspection apparatus to the process window limiting pattern locations for defect inspection.