CIRCUIT FOR GENERATION OF REFERENCE VOLTAGE AND FOR DETECTION OF UNDERVOLTAGE OF POWER-SUPPLY VOLTAGE AND CORRESPONDING METHOD

    公开(公告)号:JPH08272470A

    公开(公告)日:1996-10-18

    申请号:JP6881596

    申请日:1996-03-25

    Abstract: PROBLEM TO BE SOLVED: To provide a circuit for generating a reference voltage and simultaneously detecting the drop of a power supply voltage. SOLUTION: In this circuit for generating the reference voltage and detecting the drop of the power supply voltage provided with at least one piece of a threshold value comparator 12 provided with an input terminal IN and an output terminal and a voltage divider 14 connected between a first power supply voltage reference VS and a second voltage reference GND and connected to the input terminal IN of the comparator 12, further, the output terminal OUT of the comparator 12 is connected to the input terminal IN through at least one piece of a feedback network provided with at least one piece of a current generator CG1. The feedback network is further provided with a buffer block 13 provided with the input terminal. connected to the comparator 12 and a first output terminal DO connected to a switch SW and the switch SW is connected between the circuit node X2 of the voltage divider 14 and the second voltage reference GND.

    SLEWING SPEED CONTROL IN POWER STAGE AND OPTIMIZATION OF POWER CONSUMPTION AND DEVICE

    公开(公告)号:JPH07326953A

    公开(公告)日:1995-12-12

    申请号:JP15230995

    申请日:1995-05-25

    Abstract: PURPOSE: To optimize power consumption and switching delay by changing the operational condition of an output power transistor(TR) and attaining current absorption in accordance with a current level transmitted by a driving operational amplifier. CONSTITUTION: The driving operational amplifier 15 constituted of a differential input stage consisting of current mirrors 1 to 3 constituting a final stage, a differential TR pair N1 , N2 and a current oscillator IP. The single ends of these mirrors 1 to 3 are directly connected to the gate of the output power TR PW and the current absorption of output currents having the same level on the differential input stage is reduced in accordance with a mirror ratio. An output current from the amplifier is modulated by circuit arrangement consisting of TRs M1 , M2 , P1 to P4 , and an auxiliary current oscillator I while relating to the operation state of the circuit and the TR pair M1 , M2 is cross- coupled with the TR pair N1 , N2 . Thus a current necessary for the charging and discharging the gate node of the TR PW1 is transmitted from the operational amplifier.

    CHARGE PUMP CIRCUIT
    5.
    发明专利

    公开(公告)号:JPH06343260A

    公开(公告)日:1994-12-13

    申请号:JP4305994

    申请日:1994-02-17

    Abstract: PURPOSE: To eliminate a trouble of the conventional charging pump circuit, by replacing a diode with another element so as to prevent a voltage drop caused by the diode. CONSTITUTION: Two charge transfer devices connected in parallel, such as a pair of complementary transistors M5 and M6 as a switch, are connected between a supply node (VCC) and an output node (GND) in a circuit. As a result, a decrease in output voltage equal to a voltage drop caused by a diode in a conventional circuit can be prevented.

    EQUIPMENT AND METHOD FOR OVERLOAD PROTECTION TO PROTECT INTEGRATED CIRCUIT FROM ELECTRIC CURRENT OVERLOAD

    公开(公告)号:JPH08107629A

    公开(公告)日:1996-04-23

    申请号:JP14207495

    申请日:1995-06-08

    Abstract: PURPOSE: To independently control on-times and off-times of multiplex independent channels by a method, wherein a generating circuit which generates on times and off-times of integrated switches is connected between the input terminal of a 1st logic gate and the output of an output device. CONSTITUTION: A comparator 5, a logic gate PL1, a driver 6, a DMOS transistor Tr7 and an output terminal S1 are connected in series with the input part 2 of an overload protective device 13. The drain D1 of the transistor Tr7 is inputted to an operational amplifier 9, whose output 03 is fed back to the driver 6. A circuit A which generates on-times and off-times of integrated switches is provided between the output 04 of the amplifier 9 and the logic gate PL1. In the circuit A, the output of a capacitor C1 and a free-running type oscillator 14 is inputted to a logic gate PL2 and the on-times and off-times of respective channels are set by a storage block 16 and a counter block 15. The set on-times and off-times are inputted to the logic gate PL1. With this constitution, an interval between the on-times and off-times can be set for every channel.

    ACTIVE OVERVOLTAGE CONTROL CIRCUIT FOR INDUCTION LOAD DRIVING

    公开(公告)号:JPH01128107A

    公开(公告)日:1989-05-19

    申请号:JP25361188

    申请日:1988-10-07

    Abstract: PURPOSE: To prevent triggering characteristics from practically depending on the change of a supply voltage and a temperature by connecting a first divider to a power transistor TR, and when an overvoltage crossing the divider exceeds a limit value set in a second divider, selecting two voltage dividers and changing a state of a comparator. CONSTITUTION: To the base of the power TR Qp for driving the induction load L of a switching power converter, a driving stage by the serial circuit of the TR Qd and a resistor R7 and the serial circuit of the TR Qd and the resistor R8 is connected and switching signals are added to the base of the TR Qd. The overvoltage of a transistor crossing the TR Qp is limited by a voltage comparator by the TR Q3 , the TR Q4 , the resistor R9 and a compensation capacitor Cc. The terminal B of the comparator is connected to the intermediate node of the resistors R2 and R3 connected between the emitter and collector of the TR Qp, a voltage V1 is inputted proportionally to the voltage Vc which crosses the TR Qp and a reference voltage VREF corresponding to the preliminary setting fraction of the supply voltage Vcc is added to the other terminal A.

    METHOD AND CIRCUIT FOR DETECTION OF OPEN LOAD

    公开(公告)号:JPH08327685A

    公开(公告)日:1996-12-13

    申请号:JP12208296

    申请日:1996-05-16

    Abstract: PROBLEM TO BE SOLVED: To detect the load current accurately with high sensitivity when the load is open-circuited through simple circuitry while reducing the cost. SOLUTION: The circuit for detecting an open load comprises at least one main transistor M10 connected with a load L, and one auxiliary transistor M11 connected in parallel with the main transistor M10 between a first power supply voltage reference VS and a second voltage reference GND. The method for detecting an open load coffmprises a step for comparing a first voltage value at a terminal connected with the load of main transistor M10 with a second voltage value at a terminal of auxiliary transistor M11.

    DRIVE CIRCUIT
    9.
    发明专利

    公开(公告)号:JPH06318854A

    公开(公告)日:1994-11-15

    申请号:JP780994

    申请日:1994-01-27

    Abstract: PURPOSE: To obtain a driving circuit for field effect transistor suitable for being used at an upper stage of a half-bridge configuration, capable of being operated with a high switching rate in which no cross current appears and providing extremely high output impedance. CONSTITUTION: A first transistor M1 is connected between a gate terminal of the field effect transistor MFET1 and an negative pole GND of a voltage supply generator to turn off gate voltage of the MFET1 and the transistor M1 is driven by operational amplifiers connected to the gate terminal, a source terminal respectively by an inverted input terminal, non-inverted input terminal. Each of the MFET1 is connected with other power source M1 by switches S1, S2.

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