公开(公告)号：EP0784277A1

公开(公告)日：1997-07-16

申请号：EP96308940.4

申请日：1996-12-10

Applicant: Compaq Computer Corporation

Inventor： Wanner, Christopher C. ,  Stevens, Jeffrey C. ,  Lester, Robert A. ,  Riley, Dwight D. ,  Maguire, David J. ,  Edwards, James R.

IPC: G06F13/28 ,  G06F13/12

CPC classification number: G06F13/28 ,  G06F13/126

Abstract: A computer system having separate, yet compatible DMA controllers on a bus. Each DMA controller for controlling at least one DMA channel, each DMA controller having an independent set of registers for performing DMA operations and a configuration register for indicating channel status and designation. A DMA master for compatibly communicating with a processor and for initializing and communicating with the multiple DMA controllers.

Abstract translation: 一个计算机系统，在总线上具有独立但兼容的DMA控制器。 用于控制至少一个DMA通道的每个DMA控制器，每个DMA控制器具有用于执行DMA操作的独立的一组寄存器和用于指示通道状态和指定的配置寄存器。 DMA主机，用于与处理器进行兼容通信，并与多个DMA控制器进行初始化和通信。

公开(公告)号：EP0730235B1

公开(公告)日：2005-01-19

申请号：EP96301313.1

申请日：1996-02-27

Applicant: Compaq Computer Corporation

Inventor： Wolford, Jeff W. ,  Lester, Robert A.

IPC: G06F13/362 ,  G06F13/30 ,  G06F13/28

CPC classification number: G06F13/30 ,  G06F13/28 ,  G06F13/287 ,  G06F13/3625

公开(公告)号：EP0730235A1

公开(公告)日：1996-09-04

申请号：EP96301313.1

申请日：1996-02-27

Applicant: Compaq Computer Corporation

Inventor： Wolford, Jeff W. ,  Lester, Robert A.

IPC: G06F13/362 ,  G06F13/30 ,  G06F13/28

CPC classification number: G06F13/30 ,  G06F13/28 ,  G06F13/287 ,  G06F13/3625

Abstract: An improved DMA controller having programmable data transfer timings. Not only is the total cycle time programmable, but the active and inactive period of the cycle are also programmable. An active timing register and an inactive timing register are used in conjunction with a countdown timer to determine the active and inactive periods of the data transfer cycle. The active time period is loaded into the timer during the active phase, with the end of the active phase being indicated by the timer timing out. Next, the inactive time period is loaded into the timer, which similarly times out to indicate the end of the inactive phase of the data transfer cycle.

Abstract translation: 改进的DMA控制器，具有可编程数据传输定时。 总循环时间不仅可编程，而且循环的有效和无效周期也可编程。 一个有效的定时寄存器和一个无效的定时寄存器与倒计时定时器结合使用，以确定数据传输周期的有效和无效周期。 有效时间段在有效阶段加载到定时器中，激活阶段的结束由定时器超时指示。 接下来，将非活动时间段加载到定时器中，其类似地超时以指示数据传送周期的非活动阶段的结束。

公开(公告)号：EP0784277B1

公开(公告)日：2003-03-05

申请号：EP96308940.4

申请日：1996-12-10

Applicant: Compaq Computer Corporation

Inventor： Wanner, Christopher C. ,  Stevens, Jeffrey C. ,  Lester, Robert A. ,  Riley, Dwight D. ,  Maguire, David J. ,  Edwards, James R.

IPC: G06F13/28 ,  G06F13/12

CPC classification number: G06F13/28 ,  G06F13/126

公开(公告)号：EP0730234A3

公开(公告)日：1997-09-10

申请号：EP96301279.4

申请日：1996-02-26

Applicant: Compaq Computer Corporation

Inventor： Lester, Robert A. ,  Wolford, Jeff W.

IPC: G06F13/36 ,  G06F13/40

CPC classification number: G06F13/36

Abstract: An improved arbitration scheme including multiple arbiters for arbitrating access to a PCI bus and an ISA bus. The PCI arbiter controls access to the PCI bus by various bus masters, including the CPU/main memory subsystem, various other PCI bus masters, an enhanced DMA or EDMA controller, and an 8237-compatible DMA controller. The PCI arbiter utilizes a modified LRU arbitration scheme. Further, an SD arbiter exists to arbitrate access to the data portion (SD) of the ISA bus. The various devices that may request the SD bus include the EDMA controller, a PCI master in a PCI-to-ISA operation, the DMA controller, an ISA bus master, and the refresh controller. The SD arbiter assigns the highest priority to the PCI bus, followed by the refresh controller, EDMA controller, and DMA controller or ISA bus masters. The DMA controller includes an arbiter for arbitrating between its channels. The DMA arbiter further includes logic to ensure that the DMA controller or ISA bus master relinquishes control of the ISA bus after one arbitration cycle.

公开(公告)号：EP0730234B1

公开(公告)日：2003-02-19

申请号：EP96301279.4

申请日：1996-02-26

Applicant: Compaq Computer Corporation

Inventor： Lester, Robert A. ,  Wolford, Jeff W.

IPC: G06F13/36 ,  G06F13/40

CPC classification number: G06F13/36

公开(公告)号：EP0730234A2

公开(公告)日：1996-09-04

申请号：EP96301279.4

申请日：1996-02-26

Applicant: Compaq Computer Corporation

Inventor： Lester, Robert A. ,  Wolford, Jeff W.

IPC: G06F13/36 ,  G06F13/40

CPC classification number: G06F13/36

Abstract: An improved arbitration scheme including multiple arbiters for arbitrating access to a PCI bus and an ISA bus. The PCI arbiter controls access to the PCI bus by various bus masters, including the CPU/main memory subsystem, various other PCI bus masters, an enhanced DMA or EDMA controller, and an 8237-compatible DMA controller. The PCI arbiter utilizes a modified LRU arbitration scheme. Further, an SD arbiter exists to arbitrate access to the data portion (SD) of the ISA bus. The various devices that may request the SD bus include the EDMA controller, a PCI master in a PCI-to-ISA operation, the DMA controller, an ISA bus master, and the refresh controller. The SD arbiter assigns the highest priority to the PCI bus, followed by the refresh controller, EDMA controller, and DMA controller or ISA bus masters. The DMA controller includes an arbiter for arbitrating between its channels. The DMA arbiter further includes logic to ensure that the DMA controller or ISA bus master relinquishes control of the ISA bus after one arbitration cycle.

Abstract translation: 一种改进的仲裁方案，包括用于仲裁访问PCI总线和ISA总线的多仲裁器。 PCI仲裁器控制各种总线主机访问PCI总线，包括CPU /主存储器子系统，各种其他PCI总线主机，增强型DMA或EDMA控制器以及兼容8237的DMA控制器。 PCI仲裁器利用修改的LRU仲裁方案。 此外，存在用于仲裁对ISA总线的数据部分（SD）的访问的SD仲裁器。 可以请求SD总线的各种设备包括EDMA控制器，PCI至ISA操作中的PCI主机，DMA控制器，ISA总线主机和刷新控制器。 SD仲裁器将最高优先级分配给PCI总线，其次是刷新控制器，EDMA控制器和DMA控制器或ISA总线主机。 DMA控制器包括用于在其通道之间进行仲裁的仲裁器。 DMA仲裁器还包括确保DMA控制器或ISA总线主机在一个仲裁周期之后放弃对ISA总线的控制的逻辑。