公开(公告)号：EP0784277A1

公开(公告)日：1997-07-16

申请号：EP96308940.4

申请日：1996-12-10

Applicant: Compaq Computer Corporation

Inventor： Wanner, Christopher C. ,  Stevens, Jeffrey C. ,  Lester, Robert A. ,  Riley, Dwight D. ,  Maguire, David J. ,  Edwards, James R.

IPC: G06F13/28 ,  G06F13/12

CPC classification number: G06F13/28 ,  G06F13/126

Abstract: A computer system having separate, yet compatible DMA controllers on a bus. Each DMA controller for controlling at least one DMA channel, each DMA controller having an independent set of registers for performing DMA operations and a configuration register for indicating channel status and designation. A DMA master for compatibly communicating with a processor and for initializing and communicating with the multiple DMA controllers.

Abstract translation: 一个计算机系统，在总线上具有独立但兼容的DMA控制器。 用于控制至少一个DMA通道的每个DMA控制器，每个DMA控制器具有用于执行DMA操作的独立的一组寄存器和用于指示通道状态和指定的配置寄存器。 DMA主机，用于与处理器进行兼容通信，并与多个DMA控制器进行初始化和通信。

公开(公告)号：EP0382358A3

公开(公告)日：1993-10-06

申请号：EP90300601.3

申请日：1990-01-19

Applicant: Compaq Computer Corporation

Inventor： Wanner, Christopher C. ,  Goodrum, Alan L. ,  Culley, Paul R.

IPC: G06F13/28

CPC classification number: G06F13/28 ,  G06F12/0835

Abstract: The computer system disclosed includes a direct memory access (DMA) controller which can provide a 32 bit memory address and yet can also provide 24 bit memory address operation to remain compatible with previous systems. The DMA controller also monitors system operation and if only 24 bit address operations are occurring under the control of an external bus master or the DMA controller, the DMA controller drives the top memory address byte provided to a cache memory controller to help insure cache coherency. Additionally, the DMA controller can provide optimal time transfers for word width transfer between an odd starting memory address and an even starting input/output port.

公开(公告)号：EP0784277B1

公开(公告)日：2003-03-05

申请号：EP96308940.4

申请日：1996-12-10

Applicant: Compaq Computer Corporation

Inventor： Wanner, Christopher C. ,  Stevens, Jeffrey C. ,  Lester, Robert A. ,  Riley, Dwight D. ,  Maguire, David J. ,  Edwards, James R.

IPC: G06F13/28 ,  G06F13/12

CPC classification number: G06F13/28 ,  G06F13/126

公开(公告)号：EP0382358A2

公开(公告)日：1990-08-16

申请号：EP90300601.3

申请日：1990-01-19

Applicant: Compaq Computer Corporation

Inventor： Wanner, Christopher C. ,  Goodrum, Alan L. ,  Culley, Paul R.

IPC: G06F13/28

CPC classification number: G06F13/28 ,  G06F12/0835

Abstract: The computer system disclosed includes a direct memory access (DMA) controller which can provide a 32 bit memory address and yet can also provide 24 bit memory address operation to remain compatible with previous systems. The DMA controller also monitors system operation and if only 24 bit address operations are occurring under the control of an external bus master or the DMA controller, the DMA controller drives the top memory address byte provided to a cache memory controller to help insure cache coherency. Additionally, the DMA controller can provide optimal time transfers for word width transfer between an odd starting memory address and an even starting input/output port.

Abstract translation: 游离缺失的计算机系统盘包括直接存储器存取（DMA）控制器，它可提供一个32位存储器地址，但这样可以提供24位存储器地址操作保持与以前的系统兼容。 DMA控制器从而监视系统的操作，并且如果只有24比特的地址的操作的外部总线主机或DMA控制器的控制下发生的，DMA控制器驱动提供给高速缓冲存储器控制器的顶部存储器地址字节，以帮助保证高速缓存相关性。 此外，DMA控制器可以为奇数起始存储器地址之间的字宽传送提供最佳的时间传输，并甚至起始输入/输出端口。