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    FIELD EMITTER DEVICE, AND VEIL PROCESS FOR THE FABRICATION THEREOF
    1.
    发明申请
    FIELD EMITTER DEVICE, AND VEIL PROCESS FOR THE FABRICATION THEREOF 审中-公开
    场发射器件及其制造方法

    公开(公告)号：WO1997009731A2

    公开(公告)日：1997-03-13

    申请号：PCT/US1996013330

    申请日：1996-08-19

    Applicant: FED CORPORATION

    Inventor： FED CORPORATION ,  JONES, Gary, W. ,  ZIMMERMAN, Steven, M. ,  SILVERNAIL, Jeffrey, A. ,  JONES, Susan, K., Schwartz

    IPC: H01J00/00

    CPC classification number: H01J9/025 ,  H01J3/022 ,  H01J2201/319 ,  H01J2329/00 ,  Y10S428/938

    Abstract: A field emitter device formed by a veil process wherein a protective layer (64/66) comprising a release layer (64) is deposited on the gate electrode layer (62) for the device, with the protective layer overlying the circumscribing peripheral edge of the opening of the gate electrode layer, to protect the edge of the gate electrode layer during etching of the field emitter cavity (72) in the dielectric material layer (30) on a substrate, and during the formation of a field emitter element (40) in the cavity by depositing a field emitter material through the opening. The protective layer is readily removed subsequent to completion of the cavity etching and emitter formation steps, to yield the field emitter device. Also disclosed are various planarizing structures and methods, and current limiter compositions permitting high efficiency emission of electrons from the field emitter elements at low turn-on voltages.

    Abstract translation: 一种通过面纱工艺形成的场发射器件，其中包括释放层（64）的保护层（64/66）沉积在用于器件的栅极电极层（62）上，其中保护层覆盖在该外围边缘 在栅极电极层的开口处，以在蚀刻衬底中的电介质材料层（30）中的场致发射体空腔（72）和在形成场致发射体元件（40）期间保护栅电极层的边缘， 通过沉积通过开口的场发射体材料在腔中。 在腔蚀刻和发射极形成步骤完成之后，保护层容易去除，以产生场致发射器件。 还公开了各种平面化结构和方法，以及允许在低导通电压下从场致发射元件高效发射电子的限流器组合物。

    FLAT DISPLAY SPACER STRUCTURE AND MANUFACTURING METHOD
    3.
    发明申请
    FLAT DISPLAY SPACER STRUCTURE AND MANUFACTURING METHOD 审中-公开
    平面显示间隔结构和制造方法

    公开(公告)号：WO1996003764A1

    公开(公告)日：1996-02-08

    申请号：PCT/US1995010028

    申请日：1995-07-25

    Applicant: FED CORPORATION

    Inventor： FED CORPORATION ,  JONES, Gary, W. ,  ZIMMERMAN, Steven, M.

    IPC: H01J05/48

    CPC classification number: H01J9/242 ,  H01J29/028 ,  H01J29/864 ,  H01J31/127 ,  H01J2329/864 ,  H01J2329/866

    Abstract: A spacer structure (10) for use in a flat panel display (100), and a corresponding flat panel display article (100) are disclosed, together with an appertaining method of fabricating the spacer structure utilizing a photosensitive precursor material which is selectively irradiated, developed and etchingly processed to produce shaped standoff elements for a unitary spacer structure. The spacer structure may be dimensionally fabricated to precisely align with a selected pixel region, comprising a single pixel or an array of pixels, e.g., a color (red, blue, green) triad.

    Abstract translation: 公开了一种用于平板显示器（100）的间隔结构（10）和相应的平板显示器件（100），以及利用选择性照射的感光前体材料制造间隔结构的一种方法， 显影和蚀刻处理以产生用于整体间隔结构的成形支座元件。 间隔结构可以被尺寸制造成精确对齐所选择的像素区域，包括单个像素或像素阵列，例如，颜色（红色，蓝色，绿色）三元组。

    SELECTIVELY SHAPED FIELD EMISSION ELECTRON BEAM SOURCE, AND PHOSPHOR ARRAY FOR USE THEREWITH
    4.
    发明申请
    SELECTIVELY SHAPED FIELD EMISSION ELECTRON BEAM SOURCE, AND PHOSPHOR ARRAY FOR USE THEREWITH 审中-公开
    选择性形状场发射电子束光源，以及使用其的磷光体阵列

    公开(公告)号：WO1995026037A1

    公开(公告)日：1995-09-28

    申请号：PCT/US1995003709

    申请日：1995-03-24

    Applicant: FED CORPORATION

    Inventor： FED CORPORATION ,  JONES, Gary, W.

    IPC: H01J01/02

    CPC classification number: H01J63/04 ,  H01J1/304 ,  H01J23/06 ,  H01J29/085 ,  H01J31/127 ,  H01J2201/30403 ,  H01J2201/30426 ,  H01J2201/319 ,  H01J2237/06341 ,  H01J2237/08 ,  H01J2237/0835

    Abstract: A field emitter device (10) for selective emission of an electron and/or ion beam comprising a substrate member (12) having an array (14) of field emitter elements (16) thereon, in which the field emitter elements and/or substrate member have a varied conformation producing a beam of appropriate focused and/or directional character. Also disclosed is a display article (260) for producing an output in response to impingement of electron beams thereon, comprising a substrate member (262) on which is disposed an array of phosphor elements (264), with a diamond-like film coated on the phosphor elements to maintain the phosphor elements in position on the substrate member. Also disclosed is a field emission apparatus (210) comprising such field emitter device and display article, such as a flat panel display.

    Abstract translation: 一种用于选择性地发射电子和/或离子束的场致发射器件（10），包括在其上具有场发射极元件（16）的阵列（14）的衬底构件（12），其中场发射极元件和/或衬底 成员具有不同的构象，产生适当聚焦和/或定向角色的光束。 还公开了一种用于响应于其上的电子束的撞击而产生输出的显示制品（260），其包括衬底构件（262），荧光体元件（264）阵列上布置有金刚石薄膜 荧光体元件将磷光体元件保持在基板部件上的适当位置。 还公开了包括诸如平板显示器之类的场发射器件和显示器件的场致发射设备（210）。

    PEDESTAL EDGE EMITTER AND NON-LINEAR CURRENT LIMITERS FOR FIELD EMITTER DISPLAYS AND OTHER ELECTRON SOURCE APPLICATIONS
    6.
    发明申请
    PEDESTAL EDGE EMITTER AND NON-LINEAR CURRENT LIMITERS FOR FIELD EMITTER DISPLAYS AND OTHER ELECTRON SOURCE APPLICATIONS 审中-公开
    用于场发射显示器和其他电子源应用的PEDESTAL边缘发射极和非线性电流限制

    公开(公告)号：WO1997009730A2

    公开(公告)日：1997-03-13

    申请号：PCT/US1996013329

    申请日：1996-08-19

    Applicant: FED CORPORATION

    Inventor： FED CORPORATION ,  JONES, Gary, W. ,  ZIMMERMAN, Steven, M. ,  JONES, Susan, K., Schwartz ,  COSTA, Michael, J. ,  SILVERNAIL, Jeffrey, A.

    IPC: H01J00/00

    CPC classification number: H01J1/3042 ,  H01J2201/30423 ,  H01J2201/319

    Abstract: A microelectronic field emitter device (50) comprising a substrate (78), a conductive pedestal (64) on said substrate, and an edge emitter electrode on said pedestal, wherein the edge emitter electrode comprises an emitter cap layer (66) having an edge (68). The invention also contemplates a current limiter for a microelectronic field emitter device, which comprises a semi-insulating material selected from the group consisting of SiO, SiO+Cr (0 to 50 wt.%), SiO2 + Cr (0 to 50 wt.%), SiO + Nb, Al2O3 and SixOyNz sandwiched between an electron injector and a hole injector. Another aspect of the invention relates to a microelectronic field emitter device comprising a substrate (240), an emitter conductor (242) on such substrate, and a current limiter stack (244) formed on said substrate, such stack having a top (246) and at least one edge (248, 250), a resistive strap (266) on top of the stack, extending over the edge in electrical contact with the emitter conductor; and an emitter electrode on the current limiter stack over the resistive strap.

    Abstract translation: 一种微电子场发射器件（50），包括衬底（78），所述衬底上的导电基座（64）和所述基座上的边缘发射极，其中所述边缘发射电极包括发射极帽层（66） （68）。 本发明还考虑了一种用于微电子场发射器件的电流限制器，其包括选自SiO，SiO + Cr（0至50重量％），SiO 2 + Cr（0至50重量％）的半绝缘材料。 ％），夹在电子注入器和空穴注入器之间的SiO + Nb，Al2O3和SixOyNz。 本发明的另一方面涉及一种微电子场发射器件，其包括衬底（240），在该衬底上的发射极导体（242）以及形成在所述衬底上的限流器叠层（244），所述叠层具有顶部（246） 以及至少一个边缘（248,250），在所述堆叠的顶部上的电阻带（266），所述边缘在与所述发射极导体电接触的所述边缘上延伸; 并且电流限制器堆叠上的电阻带上的发射极电极。

    PLANARIZING PROCESS FOR FIELD EMITTER DISPLAYS AND OTHER ELECTRON SOURCE APPLICATIONS
    7.
    发明申请
    PLANARIZING PROCESS FOR FIELD EMITTER DISPLAYS AND OTHER ELECTRON SOURCE APPLICATIONS 审中-公开
    现场发射显示和其他电子源应用的平面化方法

    公开(公告)号：WO1997008727A1

    公开(公告)日：1997-03-06

    申请号：PCT/US1996013333

    申请日：1996-08-19

    Applicant: FED CORPORATION

    Inventor： FED CORPORATION ,  JONES, Gary, W. ,  ZIMMERMAN, Steven, M. ,  JONES, Susan, K., Schwartz ,  COSTA, Michael, J. ,  SILVERNAIL, Jeffrey, A.

    IPC: H01J09/02

    CPC classification number: B81C1/00611 ,  B81C2201/0126 ,  H01J9/025

    Abstract: A planarization method for use during manufacture of a microelectronic field emitter device (50), comprising applying a glass frit slurry including glass particles in a removable base, and subsequently baking to liquify the frit (300). The invention relates in another aspect to a method of making a microelectronic field emitter device, comprising the steps of: applying a patterned layer of liftoff profile resist over a substrate (326) to define emitter conductor locations; employing the patterned resist layer to form trenches (324) in the substrate at the emitter conductor locations; depositing emitter conductor metal in the trenches and over the patterned resist layer; removing the patterned resist layer; depositing a current limiter layer (334) over the conductors (322) and substrate areas between trenches; depositing a layer of emitter material; pattern masking and etching the layer of emitter material to form emitter structures (330); depositing gate dielectric; applying a patterned layer of liftoff profile resist over the gate dielectric; evaporating gate metal; and removing the patterned resist layer to define gate electrodes (332).

    Abstract translation: 一种在制造微电子场发射器件（50）期间使用的平面化方法，包括将包含玻璃颗粒的玻璃料浆料涂覆在可移除的基底中，随后烘烤以熔化玻璃料（300）。 本发明在另一方面涉及一种制造微电子场发射器件的方法，包括以下步骤：在衬底（326）上施加图案化的剥离轮廓抗蚀剂层以限定发射极导体位置; 使用图案化的抗蚀剂层在发射极导体位置处在衬底中形成沟槽（324）; 将发射极导体金属沉积在图案化的抗蚀剂层的沟槽中; 去除图案化的抗蚀剂层; 在导体（322）和沟槽之间的衬底区域上沉积限流器层（334）; 沉积一层发射体材料; 图案掩蔽和蚀刻发射极材料层以形成发射体结构（330）; 沉积栅电介质; 在栅极电介质上施加图案化的剥离轮廓抗蚀剂层; 蒸发栅极金属; 并去除图案化的抗蚀剂层以限定栅电极（332）。

    MULTILAYER EMITTER ELEMENT AND DISPLAY COMPRISING SAME
    9.
    发明申请
    MULTILAYER EMITTER ELEMENT AND DISPLAY COMPRISING SAME 审中-公开
    多层发射器元件和包含它的显示器

    公开(公告)号：WO1998013849A1

    公开(公告)日：1998-04-02

    申请号：PCT/US1997017017

    申请日：1997-09-24

    Applicant: FED CORPORATION

    Inventor： FED CORPORATION ,  JONES, Gary, W.

    IPC: H01J01/16

    CPC classification number: H01J1/3042 ,  H01J2201/30426 ,  Y10T428/2495

    Abstract: A field emitter element (10) comprising a bottom layer (14, 15) of material shaping the overall emitter element (10), and a top layer (16, 17) of low work function material or otherwise of high electron emissivity characteristic. The low work function top layer (16, 17) preferably is shaped to a sharp point. The bottom layer (14, 15) may be formed of a material such as tantalum, molybdenum, gold, or silicon (or alloys thereof), and the top layer (16, 17) may be formed of a material such as Cs, Cs2, CrSI2, Nbs2, Nb, C2O3 or SiC. In a specific aspect, at least one of the first and second emitter materials is chromium oxide (C2O3). In another variant, the first emitter material is an insulator of leaky dielectric, e.g., SiO with a 10 - 60 % C by weight based on the weight of SiO, and the second emitter material is SiO+50-90 % C by weight, based on the weight of SiO.

    Abstract translation: 包括形成整个发射体元件（10）的材料的底层（14,15）和低功函数材料的顶层（16,17）或具有高电子发射率特性的场发射极元件（10）。 低功函数顶层（16,17）优选地被成形为尖锐点。 底层（14,15）可以由诸如钽，钼，金或硅（或其合金）的材料形成，并且顶层（16,17）可以由诸如Cs，Cs2的材料形成 ，CrSI2，Nbs2，Nb，C2O3或SiC。 在具体方面，第一和第二发射体材料中的至少一个是氧化铬（C 2 O 3）。 在另一个变型中，第一发射极材料是漏电介质的绝缘体，例如基于SiO的重量，重量比为10-60％C的SiO，第二发射体材料为SiO + 50-90％C， 基于SiO的重量。

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