公开(公告)号：US11610839B2

公开(公告)日：2023-03-21

申请号：US16666808

申请日：2019-10-29

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Tung-Hsing Lee ,  Teng-Yin Lin ,  Frank W. Mont ,  Edward J. Gordon ,  Asmaa Elkadi ,  Alexander Martin ,  Won Suk Lee ,  Anvitha Shampur

IPC: H01L23/522 ,  H01L49/02 ,  H01F27/28 ,  H01F27/24 ,  H01F41/04

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to dummy fill structures and methods of manufacture. The structure includes: a passive device formed in interlevel dielectric material; and a plurality of metal dummy fill structures composed of at least one main branch and two extending legs from at least one side of the main branch, the at least two extending legs being positioned and structured to suppress eddy currents of the passive device.

公开(公告)号：US11289474B2

公开(公告)日：2022-03-29

申请号：US16853137

申请日：2020-04-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Man Gu ,  Wang Zheng ,  Teng-Yin Lin ,  Halting Wang ,  Tung-Hsing Lee

IPC: H01L21/00 ,  H01L27/11 ,  H01L27/06 ,  H01L29/78 ,  H01L49/02 ,  H01L23/66 ,  H01P3/06

Abstract: Structures including a passive device and methods of forming such structures. Multiple fins are positioned on a substrate, and an interconnect structure is positioned over the substrate. The fins contain a polycrystalline semiconductor material, and the interconnect structure includes a passive device that is positioned over the fins. The passive device may be, for example, an inductor or a transmission line.

公开(公告)号：US20210327872A1

公开(公告)日：2021-10-21

申请号：US16853137

申请日：2020-04-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Man Gu ,  Wang Zheng ,  Teng-Yin Lin ,  Haiting Wang ,  Tung-Hsing Lee

IPC: H01L27/06 ,  H01L29/78 ,  H01L49/02 ,  H01L23/66 ,  H01P3/06

Abstract: Structures including a passive device and methods of forming such structures. Multiple fins are positioned on a substrate, and an interconnect structure is positioned over the substrate. The fins contain a polycrystalline semiconductor material, and the interconnect structure includes a passive device that is positioned over the fins. The passive device may be, for example, an inductor or a transmission line.

公开(公告)号：US20250147235A1

公开(公告)日：2025-05-08

申请号：US18501602

申请日：2023-11-03

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian ,  Andreas D. Stricker ,  Abdelsalam Aboketaf ,  Judson R. Holt ,  Kevin K. Dezfulian ,  Kenneth J. Giewont ,  Alexander Derrickson ,  Won Suk Lee ,  Sujith Chandran ,  Ryan W. Sporer ,  Teng-Yin Lin

IPC: G02B6/122 ,  G02B6/13

Abstract: Structures for a photonics chip that include a photodetector and methods of forming such structures. The structure comprises a photodetector that is disposed on a substrate and that includes a light-absorbing layer. The light-absorbing layer includes a sidewall and a notch in the sidewall. The structure further comprises a waveguide core including a section adjacent to the notch in the sidewall of the light-absorbing layer.

公开(公告)号：US20240072180A1

公开(公告)日：2024-02-29

申请号：US17896711

申请日：2022-08-26

Applicant: GlobalFoundries U.S. Inc.

Inventor： Saloni Chaurasia ,  Jeffrey Johnson ,  Vibhor Jain ,  Crystal R. Kenney ,  Sudesh Saroop ,  Teng-Yin Lin ,  John J. Pekarik

IPC: H01L29/93 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/93 ,  H01L29/1095 ,  H01L29/66174

Abstract: Structures for a varactor diode and methods of forming same. The structure comprises a first semiconductor layer including a section on a substrate, a second semiconductor layer on the section of the first semiconductor layer, a third semiconductor layer on the second semiconductor layer, and a doped region in the section of the first semiconductor layer. The section of the first semiconductor layer and the doped region have a first conductivity type, and the second semiconductor layer comprises silicon-germanium having a second conductivity type opposite to the first conductivity type, and the third semiconductor layer has the second conductivity type. The doped region contains a higher concentration of a dopant of the first conductivity type than the section of the first semiconductor layer. The second semiconductor layer abuts the first section of the first semiconductor layer along an interface, and the doped region is positioned adjacent to the interface.