公开(公告)号：WO1989009534A1

公开(公告)日：1989-10-05

申请号：PCT/US1988004516

申请日：1988-12-16

Applicant: HUGHES AIRCRAFT COMPANY

Inventor： HUGHES AIRCRAFT COMPANY ,  LO, Ching-Ping ,  YEH, Kwang ,  VALLE, Manual, B.

IPC: H05K01/18

CPC classification number: B32B7/02 ,  H05K1/0271 ,  H05K1/118 ,  H05K3/0061 ,  H05K3/3442 ,  H05K3/4623 ,  H05K2201/0133 ,  H05K2201/015 ,  H05K2201/0154 ,  H05K2201/068 ,  H05K2201/09109 ,  H05K2201/09536 ,  H05K2201/10727

Abstract: A relatively thin expansion layer (18) is provided on top of the conventional printed wiring board (20). This expansion layer (18) is bonded to the printed wiring board (20) except at locations (40) underneath the footprint of the chip carrier (13) and solder joints (42). This expansion layer (18) provides forgivable expansion between the ceramic leadless chip carrier (13) and the printed wiring board (20) due to thermal expansion mismatch, to thereby reduce cracking of the solder joint (42). In an alternative embodiment, prevention of bonding underneath the chip carrier footprint is provided by a thin layer of polytetrafluoroethylene (PTFE) (39). Methods for applying the PTFE layer are disclosed.

Abstract translation: 在传统印刷电路板（20）的顶部设置相对薄的膨胀层（18）。 除了芯片载体（13）和焊点（42）的覆盖区之下的位置（40）之外，该膨胀层（18）被结合到印刷线路板（20）。 该膨胀层（18）由于热膨胀不匹配而在陶瓷无引线芯片载体（13）和印刷电路板（20）之间提供可扩展的膨胀，从而减少焊点（42）的开裂。 在替代实施例中，通过聚四氟乙烯（PTFE）薄层（39）提供防止芯片载体覆盖层之下的结合。 公开了施加PTFE层的方法。

公开(公告)号：EP0364551A1

公开(公告)日：1990-04-25

申请号：EP89904061.0

申请日：1988-12-16

Applicant: Hughes Aircraft Company

Inventor： LO, Ching-Ping ,  YEH, Kwang ,  VALLE, Manual, B.

IPC: H05K1 ,  B32B7 ,  H05K3

CPC classification number: B32B7/02 ,  H05K1/0271 ,  H05K1/118 ,  H05K3/0061 ,  H05K3/3442 ,  H05K3/4623 ,  H05K2201/0133 ,  H05K2201/015 ,  H05K2201/0154 ,  H05K2201/068 ,  H05K2201/09109 ,  H05K2201/09536 ,  H05K2201/10727

Abstract: Une couche de dilatation (18) relativement mince est disposée par-dessus la carte de circuits imprimés classique (20). Cette couche de dilatation (18) est liée à la carte de circuits imprimés (20) sauf aux endroits (40) situés au-dessous de la place occupée par le support intermédiaire (13) et les brasures (42). Cette couche de dilatation permet une dilatation tolérable entre le support intermédiaire en céramique plat (13) et la carte de circuits imprimés (20) par suite de la différence de dilatation thermique, pour ainsi réduire le fissurage des brasures (42). Dans une variante d'exécution, une mince couche de polytétrafluoroéthylène (PTFE) (39) empêche la liaison au-dessous de la place occupée par le support intermédiaire. Sont également décrits des procédés d'application de cette couche de PTFE.

公开(公告)号：EP0364551B1

公开(公告)日：1994-05-25

申请号：EP89904061.2

申请日：1988-12-16

Applicant: Hughes Aircraft Company

Inventor： LO, Ching-Ping ,  YEH, Kwang ,  VALLE, Manual, B.

IPC: H05K1/18

CPC classification number: B32B7/02 ,  H05K1/0271 ,  H05K1/118 ,  H05K3/0061 ,  H05K3/3442 ,  H05K3/4623 ,  H05K2201/0133 ,  H05K2201/015 ,  H05K2201/0154 ,  H05K2201/068 ,  H05K2201/09109 ,  H05K2201/09536 ,  H05K2201/10727

Abstract: A relatively thin expansion layer (18) is provided on top of the conventional printed wiring board (20). This expansion layer (18) is bonded to the printed wiring board (20) except at locations (40) underneath the footprint of the chip carrier (13) and solder joints (42). This expansion layer (18) provides forgivable expansion between the ceramic leadless chip carrier (13) and the printed wiring board (20) due to thermal expansion mismatch, to thereby reduce cracking of the solder joint (42). In an alternative embodiment, prevention of bonding underneath the chip carrier footprint is provided by a thin layer of polytetrafluoroethylene (PTFE) (39). Methods for applying the PTFE layer are disclosed.