公开(公告)号：CA1097823A

公开(公告)日：1981-03-17

申请号：CA310044

申请日：1978-08-25

Applicant: IBM

Inventor： ALPAUGH WARREN A ,  CANESTARO MICHAEL J ,  ELLIS THERON L

IPC: H05K3/00 ,  B08B3/08 ,  H05K3/25

Abstract: CLEANING OF HIGH ASPECT RATIO THROUGH HOLES IN MULTILAYER PRINTED CIRCUIT BOARDS A cleaning process for high aspect ratio through holes of multilayer printed circuit boards assures the removal of any loosened fiberous material or epoxy smears in the through holes and also provides an inverted "T" structure at the innerplanes of the internal conductive circuits within the printed circuit board sandwich. The inverted "T" structure helps to move the contact point between the plating of the through hole and internal circuit lines further into the circuit board, thereby eliminating the "Z" stress at the edge of the innerplane. This process is accomplished by first vapor blasting the through holes, soaking the board in a suitable solvent to loosen any fibers or smears on the circuit innerplanes of the board, removing the excess solvent from the through holes and then feeding a unilateral stream of a cleaning solution through the holes, the cleaning solution operating to remove excess fibers and smears in the through holes and to produce a slight, uniform etchback of the metal innerplanes of the printed circuit boards. Thereafter, the solution may be reduced and any excess cleaning solution is removed.

公开(公告)号：FR2356737A1

公开(公告)日：1978-01-27

申请号：FR7714015

申请日：1977-05-03

Applicant: IBM

Inventor： ALPAUGH WARREN A ,  MACUR GEORGE J ,  VLASAK GARY P

IPC: C04B41/88 ,  C23C18/16 ,  H05K3/18 ,  C23C18/28 ,  C23C18/31 ,  C23C18/34 ,  C23C18/40 ,  C23C3/02 ,  H05K3/10

Abstract: A three step seeding process with a hot water rinse and bake includes first contacting the surface of a substrate with a stannous chloride sensitizing solution, followed by a hot water rinse to remove any excess stannous chloride. Next, a palladium chloride activator is used to interact with the stannous compounds to form an adherent layer of metallic palladium particles. Thereafter, the surface is subjected to a palladium chloride/stannous chloride/HCL seeder bath which deposits a final catalytic layer on the surface and drilled through holes to facilitate the electroless plating of a metal of the substrate. A subsequent baking at a temperature between 105 DEG C and 120 DEG C sets the seeder on the substrate surface and in the through holes in the substrate.

公开(公告)号：DE69402448D1

公开(公告)日：1997-05-15

申请号：DE69402448

申请日：1994-01-27

Applicant: IBM

Inventor： ALPAUGH WARREN A ,  MARKOVICH VOYA R ,  TRIVEDI AJIT K ,  ZARR RICHARD S

IPC: H01L23/12 ,  H01L23/50 ,  H01L23/538 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K3/42 ,  H05K3/46

Abstract: A printed circuit board or card for direct chip attachment that includes at least one power core (P1), at least one signal plane (51) that is adjacent to the power core, and plated through holes (11) for electrical connection is provided. In addition, a layer of dielectric material (13) is adjacent the power core and a circuitized conductive layer (12, 14) is adjacent the dielectric material, followed by a layer of photosensitive dielectric material (15) adjacent the conductive layer. Photodeveloped blind vias (17) for subsequent connection to the power core and drilled blind vias (18) for subsequent connection to the signal plane are provided. Also provided is process for fabricating the printed circuit board or card for direct chip attachment.

公开(公告)号：DE69402448T2

公开(公告)日：1997-09-25

申请号：DE69402448

申请日：1994-01-27

Applicant: IBM

Inventor： ALPAUGH WARREN A ,  MARKOVICH VOYA R ,  TRIVEDI AJIT K ,  ZARR RICHARD S

IPC: H01L23/12 ,  H01L23/50 ,  H01L23/538 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K3/42 ,  H05K3/46

Abstract: A printed circuit board or card for direct chip attachment that includes at least one power core (P1), at least one signal plane (51) that is adjacent to the power core, and plated through holes (11) for electrical connection is provided. In addition, a layer of dielectric material (13) is adjacent the power core and a circuitized conductive layer (12, 14) is adjacent the dielectric material, followed by a layer of photosensitive dielectric material (15) adjacent the conductive layer. Photodeveloped blind vias (17) for subsequent connection to the power core and drilled blind vias (18) for subsequent connection to the signal plane are provided. Also provided is process for fabricating the printed circuit board or card for direct chip attachment.