公开(公告)号：DE69402448D1

公开(公告)日：1997-05-15

申请号：DE69402448

申请日：1994-01-27

Applicant: IBM

Inventor： ALPAUGH WARREN A ,  MARKOVICH VOYA R ,  TRIVEDI AJIT K ,  ZARR RICHARD S

IPC: H01L23/12 ,  H01L23/50 ,  H01L23/538 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K3/42 ,  H05K3/46

Abstract: A printed circuit board or card for direct chip attachment that includes at least one power core (P1), at least one signal plane (51) that is adjacent to the power core, and plated through holes (11) for electrical connection is provided. In addition, a layer of dielectric material (13) is adjacent the power core and a circuitized conductive layer (12, 14) is adjacent the dielectric material, followed by a layer of photosensitive dielectric material (15) adjacent the conductive layer. Photodeveloped blind vias (17) for subsequent connection to the power core and drilled blind vias (18) for subsequent connection to the signal plane are provided. Also provided is process for fabricating the printed circuit board or card for direct chip attachment.

公开(公告)号：DE69402448T2

公开(公告)日：1997-09-25

申请号：DE69402448

申请日：1994-01-27

Applicant: IBM

Inventor： ALPAUGH WARREN A ,  MARKOVICH VOYA R ,  TRIVEDI AJIT K ,  ZARR RICHARD S

IPC: H01L23/12 ,  H01L23/50 ,  H01L23/538 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K3/42 ,  H05K3/46

Abstract: A printed circuit board or card for direct chip attachment that includes at least one power core (P1), at least one signal plane (51) that is adjacent to the power core, and plated through holes (11) for electrical connection is provided. In addition, a layer of dielectric material (13) is adjacent the power core and a circuitized conductive layer (12, 14) is adjacent the dielectric material, followed by a layer of photosensitive dielectric material (15) adjacent the conductive layer. Photodeveloped blind vias (17) for subsequent connection to the power core and drilled blind vias (18) for subsequent connection to the signal plane are provided. Also provided is process for fabricating the printed circuit board or card for direct chip attachment.

公开(公告)号：CA2110472A1

公开(公告)日：1994-09-02

申请号：CA2110472

申请日：1993-12-01

Applicant: IBM

Inventor： BHATT ANILKUMAR C ,  BUDA LEO R ,  EDWARDS ROBERT D ,  HART PAUL J ,  INGRAHAM ANTHONY P ,  MARKOVICH VOYA R ,  MOLLA JAYNAL A ,  MURPHY RICHARD G ,  SAXENMEYER GEORGE J JR ,  WALKER GEORGE F ,  WHALEN BETTE J ,  ZARR RICHARD S

IPC: G01R31/28 ,  H01L21/60 ,  H01L21/66 ,  G01R31/26

Abstract: A method of testing semiconductor chips is disclosed. The individual semiconductor chips have I/O, power, and ground contacts. In the method of the invention a chip carrier is provided. The chip carrier has contacts corresponding to the contacts on the semiconductor chip. The carrier contacts have dendritic surfaces. The chip contacts are brought into conductive contact with the conductor pads on the chip carrier. Test signal input vectors are applied to the inputs of the semiconductor chip, and output signal vectors are recovered from the semiconductor chip. After testing, the chip may be removed from the substrate. Alternatively, the chip may be bonded through the dendritic conductor pads to the substrate after successful testing.