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1.发明授权
公开(公告)号：US3731375A
公开(公告)日：1973-05-08
申请号：US3731375D
申请日：1970-04-16
Applicant: IBM
Inventor： AGUSTA B , BARDELL P , CASTRUCCI P , HENLE R , PECORATO R
IPC: G11C11/411 , H03K3/286 , H03K3/288 , B01J17/00 , H01L1/16
CPC classification number: H03K3/286 , G11C11/4113 , H03K3/288 , Y10S438/917
Abstract: A method of making a monolithic integrated semiconductor structure that has a plurality of functionally isolated individual cells that are electrically interconnected. Each of the cells is an object of mirror image cell that is vertically, horizontally and diagonally displaced from the object cell. The plurality of cells provide a memory array with electrical components of each memory cell composed of active and passive semiconductor devices. Other importance aspects of the structure include underpass connections and active devices in a common portion of the structure which are electrically interconnected at the same node potential by means of a highly doped buried region within the common portion of the structure.
Abstract translation: 一种制造单片集成半导体结构的方法，其具有电互连的多个功能隔离的单个电池。 每个单元是从对象单元垂直，水平和对角地移位的镜像单元的对象。 多个单元提供具有由有源和无源半导体器件组成的每个存储单元的电气部件的存储器阵列。 该结构的其他重要方面包括在结构的公共部分中的地下通道连接和有源器件，其通过在结构的公共部分内的高掺杂掩埋区在相同的节点电位电互连。
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2.发明授权
公开(公告)号：US3823348A
公开(公告)日：1974-07-09
申请号：US3311970
申请日：1970-04-16
Applicant: IBM
Inventor： CASTRUCCI P , HENLE R , AGUSTA B , BARDELL P , PECORARO R
IPC: G11C11/411 , H03K3/286 , H03K3/288 , H01L5/00
CPC classification number: H03K3/286 , G11C11/4113 , H03K3/288
Abstract: A monolithic integrated semiconductor structure is described that has a plurality of functionally isolated individual cells that are electrically interconnected. Each of the cells is an object or mirror image cell that is vertically, horizontally and diagonally displaced from the object cell. The plurality of cells provide a memory array with electrical components of each memory cell composed of active and passive semiconductor devices. Other important aspects of the structure include underpass connections and active devices in a common portion of the structure which are electrically interconnected at the same node potential by means of a highly doped buried region within the common portion of the structure. In particular, a sophisticated packaging scheme for containing such a highly complex array of memory cells is disclosed.
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Patent Agency Ranking
公开(公告)号：US3723837A
公开(公告)日：1973-03-27
申请号：US3723837D
申请日：1970-09-22
Applicant: IBM
Inventor： BARDELL P
CPC classification number: H01L27/0788 , G11C5/00 , H01L27/0755 , H01L27/10 , H03K3/012
Abstract: A monolithic integrated semiconductor memory structure having both an array of bistable cells and supporting circuits for the array formed in the same semiconductor structure is bilevel powered to reduce the heat dissipation problem. Resistors used in the supporting circuits are located in common resistor beds with a means for making electrical contact, such as a diode, to the resistor bed and to provide bias during the low power standby time to the bed. The means also isolates the bias voltage supply from the bed when the signal to the resistor is increased to the high power level.
Abstract translation: 具有双稳态单元阵列和形成在相同半导体结构中的阵列的支撑电路的单片集成半导体存储器结构是双电源的，以减少散热问题。 在支持电路中使用的电阻器位于公共电阻器床中，其具有用于使电接触的装置（例如二极管）到电阻器床，并且在低功率待机时间期间向床提供偏置。 当信号到电阻器增加到高功率电平时，该装置还将偏置电压源从床层隔离开。
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公开(公告)号：US3728166A
公开(公告)日：1973-04-17
申请号：US3728166D
申请日：1967-01-11
Applicant: IBM
Inventor： BARDELL P , PECORARO R , BARSON F , BENJAMIN C
IPC: H01L21/00 , H01L21/8222 , H01L29/00 , H01L7/34 , B01J17/00
CPC classification number: H01L21/00 , H01L21/8222 , H01L29/00 , Y10S148/037 , Y10S148/085 , Y10S148/102 , Y10S148/106 , Y10S148/115 , Y10S438/975
Abstract: PATTERN. THIS PERMITS ACCURATE ALIGNMENT THAT IS NECESSARY FOR ANY SUBSEQUENT PROCESS OPERATION, WUCH AS DIFFUSION, TO BE ACCURATELY PERFORMED THEREBY INCREASING THE YIELD IN THE MANUFACTURE OF, FOR EXAMPLE, INTEGRAATED SEMICONDUCTOR DEVICES.
THIS IS A METHOD FOR ERLIABLY REPRODUCING, ON THE SURFACE OF AN EPITAXIALLY GROWN MONOCRYATALLINE LAYER, A PATTERN THAT WAS FORMED ON THE SURFACE OF THE SUBSTRATE ON WHICH THE EPITAXIAL LAYER WAS GROWN. BY USING A SUBSTRATE HAVING A (100.) CRYSTALLOGRAPHIC ORIENTATION, THE (100.) EPITAXIAL GROWN LAYER REPRODUCES THE PATTERN ON THE SUBSTRATE SURFACE DIRECTLY ABOVE THE SUBSTRATE SURFACE-
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公开(公告)号：SE345930B
公开(公告)日：1972-06-12
申请号：SE454767
申请日：1967-03-31
Applicant: IBM
Inventor： AGUSTA B , HENLE R , PECORARO R , BARDELL P , CASTRUCCI P
IPC: H01L27/08 , G11C11/411 , H03K3/286 , H03K3/288 , H01L19/00
Abstract: A monolithic integrated memory arrangement comprising, in combination, a plurality of individual memory cells, functionally isolated and electrically interconnected, in which each of said memory cells is object or corresponding to another memory cell mirroring mirror image, in vertical, horizontal and diagonal direction. (Machine-translation by Google Translate, not legally binding)
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