公开(公告)号：US3728166A

公开(公告)日：1973-04-17

申请号：US3728166D

申请日：1967-01-11

Applicant: IBM

Inventor： BARDELL P ,  PECORARO R ,  BARSON F ,  BENJAMIN C

IPC: H01L21/00 ,  H01L21/8222 ,  H01L29/00 ,  H01L7/34 ,  B01J17/00

CPC classification number: H01L21/00 ,  H01L21/8222 ,  H01L29/00 ,  Y10S148/037 ,  Y10S148/085 ,  Y10S148/102 ,  Y10S148/106 ,  Y10S148/115 ,  Y10S438/975

Abstract: PATTERN. THIS PERMITS ACCURATE ALIGNMENT THAT IS NECESSARY FOR ANY SUBSEQUENT PROCESS OPERATION, WUCH AS DIFFUSION, TO BE ACCURATELY PERFORMED THEREBY INCREASING THE YIELD IN THE MANUFACTURE OF, FOR EXAMPLE, INTEGRAATED SEMICONDUCTOR DEVICES.

THIS IS A METHOD FOR ERLIABLY REPRODUCING, ON THE SURFACE OF AN EPITAXIALLY GROWN MONOCRYATALLINE LAYER, A PATTERN THAT WAS FORMED ON THE SURFACE OF THE SUBSTRATE ON WHICH THE EPITAXIAL LAYER WAS GROWN. BY USING A SUBSTRATE HAVING A (100.) CRYSTALLOGRAPHIC ORIENTATION, THE (100.) EPITAXIAL GROWN LAYER REPRODUCES THE PATTERN ON THE SUBSTRATE SURFACE DIRECTLY ABOVE THE SUBSTRATE SURFACE

公开(公告)号：US3823348A

公开(公告)日：1974-07-09

申请号：US3311970

申请日：1970-04-16

Applicant: IBM

Inventor： CASTRUCCI P ,  HENLE R ,  AGUSTA B ,  BARDELL P ,  PECORARO R

IPC: G11C11/411 ,  H03K3/286 ,  H03K3/288 ,  H01L5/00

CPC classification number: H03K3/286 ,  G11C11/4113 ,  H03K3/288

Abstract: A monolithic integrated semiconductor structure is described that has a plurality of functionally isolated individual cells that are electrically interconnected. Each of the cells is an object or mirror image cell that is vertically, horizontally and diagonally displaced from the object cell. The plurality of cells provide a memory array with electrical components of each memory cell composed of active and passive semiconductor devices. Other important aspects of the structure include underpass connections and active devices in a common portion of the structure which are electrically interconnected at the same node potential by means of a highly doped buried region within the common portion of the structure. In particular, a sophisticated packaging scheme for containing such a highly complex array of memory cells is disclosed.

公开(公告)号：US3729316A

公开(公告)日：1973-04-24

申请号：US3729316D

申请日：1970-02-17

Applicant: IBM

Inventor： PECORARO R ,  CASTRUCCI P ,  HADDAD N

IPC: H05K3/00 ,  G03F1/00 ,  H01L21/00 ,  H01L21/027 ,  G03C5/00

CPC classification number: G03F1/60 ,  H01L21/00

Abstract: A PROCESS FOR MAKING A PHOTOGRAPHIC OPTICAL GLASS MASK THAT IS USED IN SILICON INTEGRAED CIRCUIT WAFER PROCESSING. AN OPTICAL GLASS MASK IS MADE BY MEANS OF A STEP AND REPEAT CAMERA. DISPLACEMENT ERROR WHICH IS CAUSED BY THE DIFFERENCE IN CEFFICIENTS OF EXPANSION BETWEEN THE MICROSET SCALE OF THE STEP AND REPEAT CAMERA AND THE PHOTOGRAPHIC OPTICAL MASK, IS MINIMIZED BY USING THE SAME MATERIAL FOR BOTH ELEMENTS. FURTHER DISPLACEMENT ERROR CAUSED BY THERMAL MISMATCH OF THE OPTICAL GLASS MASK AND THE SILICON WAFER IS MINIMIZED BY USING A BOROSILICATE GLASS MASK HAVING A LINEAR COEFFICIENT OF EXPANSION OF 3.5X10-6/DEGREES C., WHICH SUBSTANTIALLY MATCHES HE LINEAR COEFFICIENT OF EXPANSION OF THE SILICON WAFER MATERIAL.

Abstract translation: 1323647 Photo-masks国际商业公司1971年4月19日[1970年2月17日] 21760/71标题G2M制备半导体集成电路的光掩模包括布置在硼硅酸盐玻璃支撑构件上的电路图案。 主面罩可以通过步骤和重复照相机制成，并用于联系打印副主席，后者又用于联系打印工作台面具，2个主人和面具都有硼硅酸盐玻璃支架。

公开(公告)号：SE345930B

公开(公告)日：1972-06-12

申请号：SE454767

申请日：1967-03-31

Applicant: IBM

Inventor： AGUSTA B ,  HENLE R ,  PECORARO R ,  BARDELL P ,  CASTRUCCI P

IPC: H01L27/08 ,  G11C11/411 ,  H03K3/286 ,  H03K3/288 ,  H01L19/00

Abstract: A monolithic integrated memory arrangement comprising, in combination, a plurality of individual memory cells, functionally isolated and electrically interconnected, in which each of said memory cells is object or corresponding to another memory cell mirroring mirror image, in vertical, horizontal and diagonal direction. (Machine-translation by Google Translate, not legally binding)