公开(公告)号：CH617523A5

公开(公告)日：1980-05-30

申请号：CH532977

申请日：1977-04-28

Applicant: IBM

Inventor： BIRNEY RICHARD EUGENE ,  DAVIS MICHAEL IAN ,  GRAYBIEL LYNN ALLAN ,  KAHN SAMUEL ,  OSBORNE WILLIAM STEESE ,  HOOD ROBERT ALLEN ,  BOURKE DONALL GERRAID

IPC: G06F12/02 ,  G06F9/36

Abstract: In a data processing system with translation of the logic addresses, predetermined in the programs, into the physical addresses necessary for memory access, special devices are provided by means of which flexible allocation of address areas for various categories of information or various types of programs is possible. The address translator arrangement has a separate translator unit (stack 0... stack 7) for each address area. In addition, an arrangement (20...35) for storing various address keys for various categories of information and for outputting one of these keys each on the basis of present memory access control signals is provided. One of the translator units is then in each case selected with the aid of the output address key by means of an additional selection device (40). This makes it possible to obtain different physical addresses from the same logic address during the translation, dependently on which category of information is to be accessed at the time and dependently on the address key in each case allocated to the category of information.