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    MEMORY CELL
    2.
    发明专利
    MEMORY CELL 失效

    公开(公告)号：JPH10229175A

    公开(公告)日：1998-08-25

    申请号：JP824898

    申请日：1998-01-20

    Applicant: IBM

    Inventor： STUART MACRESTARR BURNS JR ,  HANAFI HUSSEIN I ,  JEFFREY J WELSER

    IPC: H01L21/8242 ,  H01L21/8247 ,  H01L27/108 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

    Abstract: PROBLEM TO BE SOLVED: To provide a high-density array of vertical semiconductor elements having pillars, and a method of forming it. SOLUTION: An array has a column of bit lines 220, and a row of word lines 225. The gate of a transistor functions as a word line, and a source region 215 or a drain region 240 functions as a bit line. The array also has a vertical pillar 230, each of which has a channel made between the source region and the drain region. Two transistors can be made per pillar. The source region is arranged under the pillar, being self-aligned. The source regions of the adjacent bit lines are separated from each other, without increasing the cell size. The array structure can be used as a DRAM, EEPROM, or a flash memory.

    Buried biasing wells in fets
    4.
    发明专利
    Buried biasing wells in fets 有权
    在FET中的BLEIED BIASING WELLS

    公开(公告)号：JP2006093694A

    公开(公告)日：2006-04-06

    申请号：JP2005257269

    申请日：2005-09-06

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： HANAFI HUSSEIN I ,  EDWARD J NOWAKU

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/105 ,  H01L29/0653 ,  H01L29/66628 ,  H01L29/7834

    Abstract: PROBLEM TO BE SOLVED: To provide a novel structure in a semiconductor device to eliminate or reduce leakage current and junction capacitance. SOLUTION: A structure of a semiconductor device and method of fabricating the same is disclosed. The semiconductor structure includes first and second source/drain regions; a channel region disposed between the first and second source/drain regions; a buried well region in physical contact with the channel region; and buried barrier regions disposed between the buried well region and the first source/drain region and disposed between the buried well region and the second source/drain region, wherein the buried barrier regions are adapted for preventing current leakage and dopant diffusion between the buried well region and the first source/drain region, and current leakage and dopant diffusion between the buried well region and the second source/drain region. COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：为了提供半导体器件中的新颖结构以消除或减少漏电流和结电容。 解决方案：公开了半导体器件的结构及其制造方法。 半导体结构包括第一和第二源极/漏极区域; 设置在所述第一和第二源极/漏极区之间的沟道区; 与通道区域物理接触的掩埋阱区域; 以及埋置的阻挡区域，其设置在所述掩埋阱区域和所述第一源极/漏极区域之间并且设置在所述掩埋阱区域和所述第二源极/漏极区域之间，其中所述掩埋阻挡区域适于防止所述掩埋阱之间的电流泄漏和掺杂剂扩散 区域和第一源极/漏极区域，以及掩埋阱区域和第二源极/漏极区域之间的电流泄漏和掺杂剂扩散。 版权所有（C）2006，JPO＆NCIPI

    FIELD EFFECT TRANSISTOR EQUIPPED WITH VERTICAL GATE SIDE WALL AND MANUFACTURE THEREOF
    7.
    发明专利
    FIELD EFFECT TRANSISTOR EQUIPPED WITH VERTICAL GATE SIDE WALL AND MANUFACTURE THEREOF 失效

    公开(公告)号：JPH11317524A

    公开(公告)日：1999-11-16

    申请号：JP3111199

    申请日：1999-02-09

    Applicant: IBM

    Inventor： BOYD DIANE C ,  BURNS STUART M ,  HANAFI HUSSEIN I ,  TAUR YUAN ,  WILLE WILLIAM C

    IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

    Abstract: PROBLEM TO BE SOLVED: To enable a field effect transistor to be accurately specified in channel length, lessened in source and drain resistance, and minimized in overlap capacitance, by a method wherein a gate hole is demarcated on a dielectric stack, an attached side wall layer is removed from a horizontal plane, and the gate hole is filled up with a gate conductor. SOLUTION: An etching window which is nearly equal in lateral dimension to a gate pillar that is specified in dimensions by a resist mask is provided to a dielectric stack which comprises nitride layers 31 and 38. An RIE process for forming a gate hole is used for transferring the etching window to the dielectric stack. Then, the gate hole is demarcated-by an RIE method, a side wall layer is attached and then removed from a horizontal plane. By this setup, the gate hole is lessened in length by a residual side wall spacer 61. Then, polysilicon is deposited inside the gate hole and on a dielectric stack uppermost layer 38, and the dielectric stack uppermost layer 38 is exposed by flattening the deposited polysilicon.

    Method for making field effect transistors having sub-lithographic gates with vertical side walls
    8.
    发明专利
    Method for making field effect transistors having sub-lithographic gates with vertical side walls 未知

    公开(公告)号：SG71909A1

    公开(公告)日：2000-04-18

    申请号：SG1999000606

    申请日：1999-02-15

    Applicant: IBM

    Inventor： BOYD DIANE C ,  BURNS STUART M ,  HANAFI HUSSEIN I ,  TAUR YUAN ,  WILLE WILLIAM C

    IPC: H01L21/033 ,  H01L21/28 ,  H01L21/336 ,  H01L21/762 ,  H01L29/423 ,  H01L29/78

    Abstract: A method for the formation of field effect transistors (FETs), and more particularly metal oxide field effect transistors (MOSFETs), comprising the steps of: forming a dielectric stack on a semiconductor structure; defining an etch window on the dielectric stack; defining a gate hole in the dielectric stack by transferring the etch window into the dielectric stack using a reactive ion etching (RIE) process; depositing a side wall layer; removing the side wall layer from horizontal surfaces of the dielectric stack and gate hole such that side wall spacers remain which reduce the lateral size of the gate hole; depositing a gate conductor such that it fills the gate hole; removing the gate conductor covering the portions of the semiconductor structure surrounding the gate hole; removing at least part of the dielectric stack; and removing the side wall spacers.

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