公开(公告)号：JPH11317524A

公开(公告)日：1999-11-16

申请号：JP3111199

申请日：1999-02-09

Applicant: IBM

Inventor： BOYD DIANE C ,  BURNS STUART M ,  HANAFI HUSSEIN I ,  TAUR YUAN ,  WILLE WILLIAM C

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To enable a field effect transistor to be accurately specified in channel length, lessened in source and drain resistance, and minimized in overlap capacitance, by a method wherein a gate hole is demarcated on a dielectric stack, an attached side wall layer is removed from a horizontal plane, and the gate hole is filled up with a gate conductor. SOLUTION: An etching window which is nearly equal in lateral dimension to a gate pillar that is specified in dimensions by a resist mask is provided to a dielectric stack which comprises nitride layers 31 and 38. An RIE process for forming a gate hole is used for transferring the etching window to the dielectric stack. Then, the gate hole is demarcated-by an RIE method, a side wall layer is attached and then removed from a horizontal plane. By this setup, the gate hole is lessened in length by a residual side wall spacer 61. Then, polysilicon is deposited inside the gate hole and on a dielectric stack uppermost layer 38, and the dielectric stack uppermost layer 38 is exposed by flattening the deposited polysilicon.

公开(公告)号：JPH11274496A

公开(公告)日：1999-10-08

申请号：JP3112599

申请日：1999-02-09

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレイション

Inventor： DAINE C BOYD ,  BURNS STUART M ,  HUSSEIN I HANAPHY ,  TAUR YUAN ,  WILLE WILLIAM C

IPC: H01L21/76 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/08 ,  H01L29/78

CPC classification number: H01L29/66583 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823481 ,  H01L29/66537

Abstract: PROBLEM TO BE SOLVED: To form a threshold adjusting implant located only under a channel, by implanting a threshold adjusting dopant through a gate hole or a punch- through adjusting dopant after defining the gate hole on a dielectric stack.
SOLUTION: After defining a gate hole 40 in a dielectric stack, either a threshold adjusting dopant or a punch-through dopant is implanted through the hole 40. Since the hole 40 allows the dopant to reach only a region just under the hole 40, the implantation of the dopant is effected by an accurately controlled method. The dimensions and shape of the hole 40 determine the dimensions and shape of the threshold adjusting implant. Therefore, the threshold adjusting implant located only under a channel can be formed.
COPYRIGHT: (C)1999,JPO

Abstract translation: 要解决的问题：为了形成仅位于通道下方的阈值调节植入物，通过在限定电介质叠层上的栅极孔之后通过栅极孔或穿通调节掺杂剂注入阈值调节掺杂剂。 解决方案：在电介质叠层中定义栅极孔40之后，通过孔40注入阈值调节掺杂剂或穿通掺杂剂。由于孔40允许掺杂剂仅到达孔40正下方的区域，因此， 通过精确控制的方法实现掺杂剂的注入。 孔40的尺寸和形状决定了阈值调节植入物的尺寸和形状。 因此，可以形成仅位于通道下方的阈值调节植入物。

公开(公告)号：JP2004006310A

公开(公告)日：2004-01-08

申请号：JP2003109122

申请日：2003-04-14

Applicant: IBM

Inventor： VOLANT RICHARD P ,  ANGELL DAVID ,  CANAPERI DONALD F ,  KOCIS JOSEPH T ,  PETRARCA KEVIN S ,  STEIN KENNETH JAY ,  WILLE WILLIAM C

IPC: B81B3/00 ,  B81C1/00 ,  H01H49/00 ,  H01H59/00

Abstract: PROBLEM TO BE SOLVED: To provide a structure and a manufacturing method of a microelectric mechanical switch (MEMS) device provided with a self-alignment spacer or a bump. SOLUTION: The spacers arranged having the optimum size so as to make to the minimum a problem caused by stiction by functioning as restricting mechanism concerning the switch are designed. The spacers are manufactured by using the typically standard semi-conductor technology used for manufacturing a CMOS device. This method to manufacture these spacers does not need an additional deposition, excessive lithography process, and an additional etching. COPYRIGHT: (C)2004,JPO

公开(公告)号：JPH11186243A

公开(公告)日：1999-07-09

申请号：JP28213898

申请日：1998-10-05

Applicant: IBM

Inventor： ARMACOST MICHAEL D ,  CONLEY WILLARD E ,  COTLER-WAGNER TINA J ,  DELLAGUARDIA RONALD A ,  DOBUZINSKY DAVID M ,  PASSOW MICHAEL L ,  WILLE WILLIAM C

IPC: G03F7/40 ,  G03F7/033 ,  G03F7/039 ,  H01L21/027 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/311

Abstract: PROBLEM TO BE SOLVED: To provide a resist prescription which is capable of reducing blisters that are generated in a reactive ion etching process to increase the deposit of a resin by-product. SOLUTION: Gaseous fluorocarbon etchant is excited by energy large enough to generate a plasma of high density, wherein the ratio of carbon to fluorine of the etchant is at least 0.33. A resist 12 which is least blistered under the above conditions contains resin binder of terpolymer besides a usual optically active component, wherein the resin binder is composed of (a) a first unit which contains groups unstable to acid, (b) a second unit which does not contain reactive groups and hydroxyl groups, and (c) a third unit which is conducive to development by an aqueous developing agent. The resist, layer 12 on a silicon oxide layer 14 is patterned, and plasma of high density is introduced onto the silicon oxide layer 14, and at least an opening 18 is provided to the silicon oxide layer 14 by etching.

公开(公告)号：DE69807621D1

公开(公告)日：2002-10-10

申请号：DE69807621

申请日：1998-06-26

Applicant: SIEMENS AG ,  IBM

Inventor： LEVY MAX G ,  FIEGL BERNHARD ,  BERGNER WOLFGANG ,  GOTH GEORGE R ,  PARRIES PAUL ,  SENDELBACH MATTHEW J ,  WANG TING-HAO ,  WILLE WILLIAM C ,  WITTMANN JUERGEN

IPC: H01L21/302 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/76 ,  H01L21/321

Abstract: A method for preventing CMP-induced (chemical-mechanical polish) damage to a substrate disposed below a pad nitride layer of a mesa. The pad nitride layer is disposed below a conformally deposited dielectric layer. The dielectric layer is disposed below a conformally deposited polysilicon layer. The method includes planarizing the polysilicon layer down to at least a surface of the dielectric layer using the CMP to expose a first region of the dielectric layer. The method further includes etching partially through the first region of the dielectric layer using first etch parameters. The first etch parameters include an etchant source gas that is substantially selective to the pad nitride layer to prevent the pad nitride layer from being etched through even in the presence of a CMP defect. Additionally, there is also included removing the polysilicon layer after the etching partially through the first region of the dielectric layer.

公开(公告)号：SG152150A1

公开(公告)日：2009-05-29

申请号：SG2008074650

申请日：2008-10-03

Applicant: CHARTERED SEMICONDUCTOR MFG ,  SAMSUNG ELECTRONICS CO LTD ,  IBM

Inventor： JUNG KIM JUN ,  WIDODO JOHNNY ,  CHAN KIM JOO ,  ZHAO LUN ,  EON PARK JAE ,  WILLE WILLIAM C ,  CONTI RICHARD ANTHONY ,  BIAO ZUO

Abstract: Methods of forming integrated circuit devices include forming a trench in a surface of semiconductor substrate and filling the trench with an electrically insulating region having a seam therein. The trench may be filled by depositing a sufficiently thick electrically insulating layer on sidewalls and a bottom of the trench. Curing ions are then implanted into the electrically insulating region at a sufficient energy and dose to reduce a degree of atomic order therein. The curing ions may be ones selected from a group consisting of nitrogen (N), phosphorus (P), boron (B), arsenic (As), carbon (C), argon (Ar), germanium (Ge), helium (He), neon (Ne) and xenon (Xe). These curing ions may be implanted at an energy of at least about 80 KeV and a dose of at least about 5x1014 ions/cm2. The electrically insulating region is then annealed at a sufficient temperature and for a sufficient duration to increase a degree of atomic order within the electrically insulating region. Figure 1E

公开(公告)号：SG138522A1

公开(公告)日：2008-01-28

申请号：SG2007030810

申请日：2007-04-27

Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： ZHIJIONG LUO ,  NG HUNG Y ,  ROVEDO NIVO ,  NGUYEN PHUNG T ,  WILLE WILLIAM C ,  LINSAY RICHARD ,  LUN ZHAO ,  FU CHONG YUNG ,  PANDA SIDDHARTHA

Abstract: A semiconductor structure includes a base semiconductor substrate having a doped region located therein, and an epitaxial region located over the doped region. The semiconductor structure also includes a final isolation region located with the doped region and the epitaxial region. The final isolation region has a greater linewidth within the doped region than within the epitaxial region. A method for fabricating the semiconductor structure provides for forming the doped region prior to the epitaxial region. The doped region may be formed with reduced well implant energy and reduced lateral straggle. The final isolation region with the variable linewidth provides a greater effective isolation depth than an actual trench isolation depth.

公开(公告)号：DE69821458D1

公开(公告)日：2004-03-11

申请号：DE69821458

申请日：1998-11-19

Applicant: IBM

Inventor： ARMACOST MICHAEL D ,  CONLEY WILLARD E ,  COTLER-WAGNER TINA J ,  DELLAGUARDIA RONALD A ,  DOBUZINSKY DAVID M ,  PASSOW MICHAEL L ,  WILLE WILLIAM C

IPC: G03F7/40 ,  G03F7/033 ,  G03F7/039 ,  H01L21/027 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768

Abstract: A resist formulation minimizes blistering during reactive ion etching processes resulting in an increased amount of polymer by-product deposition. Such processes involve exciting a gaseous fluorocarbon etchant with sufficient energy to form a high-density plasma, and the use of an etchant having a carbon-to-fluorine ratio of at least 0.33. In addition to a conventional photoactive component, resists which minimize blistering under these conditions include a resin binder which is a terpolymer having: (a) units that contain acid-labile groups; (b) units that are free of reactive groups and hydroxyl groups; and (c) units that contribute to aqueous developability of the photoresist. After the photoresist is patterned on the silicon oxide layer and the high-density plasma is formed, the high-density plasma is introduced to the silicon oxide layer to etch at least one opening in the silicon oxide layer. Preferably, the terpolymer is made up of about 70% 4-hydroxystyrene, about 20% styrene, and about 10% t-butylacrylate.

公开(公告)号：DE69807621T2

公开(公告)日：2003-11-27

申请号：DE69807621

申请日：1998-06-26

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： LEVY MAX G ,  FIEGL BERNHARD ,  BERGNER WOLFGANG ,  GOTH GEORGE R ,  PARRIES PAUL ,  SENDELBACH MATTHEW J ,  WANG TING-HAO ,  WILLE WILLIAM C ,  WITTMANN JUERGEN

IPC: H01L21/302 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/76 ,  H01L21/321

Abstract: A method for preventing CMP-induced (chemical-mechanical polish) damage to a substrate disposed below a pad nitride layer of a mesa. The pad nitride layer is disposed below a conformally deposited dielectric layer. The dielectric layer is disposed below a conformally deposited polysilicon layer. The method includes planarizing the polysilicon layer down to at least a surface of the dielectric layer using the CMP to expose a first region of the dielectric layer. The method further includes etching partially through the first region of the dielectric layer using first etch parameters. The first etch parameters include an etchant source gas that is substantially selective to the pad nitride layer to prevent the pad nitride layer from being etched through even in the presence of a CMP defect. Additionally, there is also included removing the polysilicon layer after the etching partially through the first region of the dielectric layer.

公开(公告)号：SG71909A1

公开(公告)日：2000-04-18

申请号：SG1999000606

申请日：1999-02-15

Applicant: IBM

Inventor： BOYD DIANE C ,  BURNS STUART M ,  HANAFI HUSSEIN I ,  TAUR YUAN ,  WILLE WILLIAM C

IPC: H01L21/033 ,  H01L21/28 ,  H01L21/336 ,  H01L21/762 ,  H01L29/423 ,  H01L29/78

Abstract: A method for the formation of field effect transistors (FETs), and more particularly metal oxide field effect transistors (MOSFETs), comprising the steps of: forming a dielectric stack on a semiconductor structure; defining an etch window on the dielectric stack; defining a gate hole in the dielectric stack by transferring the etch window into the dielectric stack using a reactive ion etching (RIE) process; depositing a side wall layer; removing the side wall layer from horizontal surfaces of the dielectric stack and gate hole such that side wall spacers remain which reduce the lateral size of the gate hole; depositing a gate conductor such that it fills the gate hole; removing the gate conductor covering the portions of the semiconductor structure surrounding the gate hole; removing at least part of the dielectric stack; and removing the side wall spacers.