公开(公告)号：JP2005217420A

公开(公告)日：2005-08-11

申请号：JP2005021358

申请日：2005-01-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： EDELSTEIN DANIEL C ,  COLBURN MATTHEW E ,  COONEY EDWARD C III ,  DALTON TIMOTHY J ,  FITZSIMMONS JOHN A ,  GAMBINO JEFFREY P ,  HUANG ELBERT E ,  LANE MICHAEL W ,  MCGAHAY VINCENT J ,  NICHOLSON LEE M ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH ,  SANKARAN SUJATHA ,  SHAW THOMAS M ,  SIMON ANDREW H ,  STAMPER ANTHONY K

IPC: H01L21/033 ,  H01L21/302 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532 ,  H01L29/40

CPC classification number: B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device of high strength that lowers an effective dielectric constant k eff , maintains an inter-level vertical capacity in an interconnection at a low level and a manufacturing method of the same. SOLUTION: The method of manufacturing the device comprises a step for providing a structure having an insulating layer 120 of at least one interconnection 130 and a step for forming a sublithographic template mask 150 on the insulating layer. A sublithographic feature 135a is formed in the vicinity of at least one intereconnection by performing etching on the insulating layer through the sublithographic template mask using a selective etching step. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供一种降低有效介电常数k eff 的高强度半导体器件，将互连中的级间垂直容量保持在低水平，并且制造方法 一样的。 解决方案：制造该器件的方法包括提供具有至少一个互连130的绝缘层120和在绝缘层上形成亚光刻模板掩模150的步骤的结构的步骤。 通过使用选择性蚀刻步骤，通过通过亚光刻模板掩模对绝缘层进行蚀刻，在至少一个相互连接附近形成亚光刻部件135a。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2005268783A

公开(公告)日：2005-09-29

申请号：JP2005066836

申请日：2005-03-10

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： COLBURN MATTHEW E ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH

IPC: H01J9/14 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/48 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L21/7682 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method for fabricating a nanocolumnar airbridge structure in a Very-Large Scale Integrated (VLSI) and Ultra-Large Scale Integrated (ULSI) devices, and also to provide high performance packaging. SOLUTION: A method for producing a low k, ultra-low k, and super ultra-low-k multilayer interconnect structures on a substrate, in which the interconnect line structure bodies are separated laterally by a dielectric with vertically oriented nanoscale voids, formed by perforating the voids using sub-optical lithography patterning and etching techniques and closing off the tops of the perforations by a dielectric deposition step. The lines are supported by either solid or patterned dielectric features underneath. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种在超大规模集成（VLSI）和超大规模集成（ULSI）装置中制造纳米柱式气桥结构的方法，并且还提供高性能包装。 解决方案：一种用于在衬底上制造低k，超低k和超超低k多层互连结构的方法，其中互连线结构体由具有垂直取向的纳米尺度空隙的电介质横向分离 通过使用亚光学光刻图案和蚀刻技术对空隙进行穿孔而形成，并通过介电沉积步骤封闭穿孔的顶部。 这些线由下面的固体或图案化电介质特征支撑。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004214648A

公开(公告)日：2004-07-29

申请号：JP2003421653

申请日：2003-12-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： COLBURN MATTHEW E ,  HUANG ELBERT E ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH ,  SAENGER KATHERINE L

IPC: H01L23/12 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76808 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming in-layer and interlayer air bridge structures, in a large scale integrated circuit (VLSI) device, a very large scale integrated circuit (ULSI) device, and a high-performance package. SOLUTION: The method of forming low k (dielectric constant) and ultra-low k multilayer mutual connections on a substrate is provided with a process to form a pair of mutual connection, separated along a side face by an air gap and a support layer in a via level of a dual damascene structure which exists only under a metal wiring, a process to remove a sacrificial dielectric through a holed bridge layer to connect an upper surface of the mutual connection along the side face, a process of executing a multilayer level extraction of the sacrificial layer, a process of sealing the bridge by a controlled method, and a process of reducing the effective dielectric constant of a film holed by using a patterning technology of a quasi-optical lithography. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：WO2012128843A3

公开(公告)日：2013-03-14

申请号：PCT/US2012023065

申请日：2012-01-30

Applicant: IBM ,  YIN YUNGPENG ,  ARNOLD JOHN C ,  COLBURN MATTHEW E ,  BURNS SEAN D

Inventor： YIN YUNGPENG ,  ARNOLD JOHN C ,  COLBURN MATTHEW E ,  BURNS SEAN D

IPC: H01L21/027

CPC classification number: H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139

Abstract: An improved method of performing sidewall spacer image transfer is presented. The method includes forming a set of sidewall spacers (109a) next to a plurality of mandrels (106a), the set of sidewall spacers being directly on top of a hard-mask layer (105); transferring image of at least a portion of the set of sidewall spacers to the hard- mask layer to form a device pattern (105a); and transferring the device pattern from the hard- mask layer to a substrate (101) underneath the hard-mask layer.

Abstract translation: 提出了一种执行侧壁间隔图像转移的改进方法。 该方法包括在多个心轴（106a）旁边形成一组侧壁间隔物（109a），该组侧壁间隔物直接位于硬掩模层（105）的顶部上。 将所述一组侧壁间隔物的至少一部分图像转印到所述硬掩模层以形成器件图案（105a）; 以及将所述装置图案从所述硬掩模层转移到所述硬掩模层下方的基板（101）。

公开(公告)号：DE602005007776D1

公开(公告)日：2008-08-07

申请号：DE602005007776

申请日：2005-10-18

Applicant: IBM

Inventor： COLBURN MATTHEW E ,  MARTIN YVES C ,  RETTNER CHARLES T ,  VAN KESSEL THEODORE G ,  WICKRAMASINGHE HEMATHA K

IPC: G03F7/00

Abstract: A method (and resultant structure) of forming a plurality of masks, includes creating a reference template, using imprint lithography to print at least one reference template alignment mark on all of a plurality of mask blanks for a given chip set, and printing sub-patterns on each of the plurality of mask blanks, and aligning the sub-patterns to the at least one reference template alignment mark.

公开(公告)号：DE112012000932B4

公开(公告)日：2018-05-24

申请号：DE112012000932

申请日：2012-01-30

Applicant: IBM

Inventor： YIN YUNGPENG ,  ARNOLD JOHN C ,  COLBURN MATTHEW E ,  BURNS SEAN D

IPC: H01L21/027

Abstract: Verfahren, aufweisend:Bilden einer Gruppe von Seitenwand-Abstandhaltern (109a) neben mehreren Dornen (106a), wobei sich die Gruppe von Seitenwand-Abstandhaltern direkt auf einer Hartmaskenschicht (105) befindet;Übertragen eines Bildes zumindest eines Abschnitts der Gruppe von Seitenwand-Abstandhaltern auf die Hartmaskenschicht, um eine Einheitsstruktur (105a) zu bilden;Übertragen der Einheitsstruktur von der Hartmaskenschicht auf ein Substrat (101) unterhalb der Hartmaskenschicht; undBilden einer Photoresist-Sperrmaske (112a), wobei die Photoresist-Sperrmaske nur den zumindest einen Abschnitt der Gruppe von Seitenwand-Abstandhaltern frei lässt und den Rest der Gruppe von Seitenwand-Abstandhaltern bedeckt,wobei die Hartmaskenschicht eine zweite Hartmaskenschicht ist und wobei das Übertragen der Einheitsstruktur von der Hartmaskenschicht auf das Substrat ferner das Übertragen der Einheitsstruktur auf eine erste Hartmaskenschicht (103) umfasst, wobei sich die erste Hartmaskenschicht unterhalb der zweiten Hartmaskenschicht befindet und durch eine Planarisierungsschicht (104) von dieser getrennt ist.

公开(公告)号：CA2843399C

公开(公告)日：2019-12-10

申请号：CA2843399

申请日：2012-01-30

Applicant: IBM

Inventor： YIN YUNPENG ,  ARNOLD JOHN C ,  COLBURN MATTHEW E ,  BURNS SEAN D

IPC: H01L21/027

Abstract: An improved method of performing sidewall spacer image transfer is presented. The method includes forming a set of sidewall spacers (109a) next to a plurality of mandrels (106a), the set of sidewall spacers being directly on top of a hard-mask layer (105); transferring image of at least a portion of the set of sidewall spacers to the hard- mask layer to form a device pattern (105a); and transferring the device pattern from the hard- mask layer to a substrate (101) underneath the hard-mask layer.

公开(公告)号：DE112012000932T5

公开(公告)日：2014-01-09

申请号：DE112012000932

申请日：2012-01-30

Applicant: IBM

Inventor： YIN YUNGPENG ,  ARNOLD JOHN C ,  COLBURN MATTHEW E ,  BURNS SEAN D

IPC: H01L21/027

Abstract: Es wird ein verbessertes Verfahren zur Durchführung einer Seitenwand-Abstandhalter-Bildübertragung bereitgestellt. Das Verfahren umfasst das Bilden einer Gruppe von Seitenwand-Abstandhaltern (109a) neben mehreren Dornen (106a), wobei sich die Gruppe von Seitenwand-Abstandhaltern direkt auf einer Hartmaskenschicht (105) befindet; das Übertragen eines Bildes zumindest eines Abschnitts der Gruppe von Seitenwand-Abstandhaltern auf die Hartmaskenschicht, um eine Einheitsstruktur (105a) zu bilden; und das Übertragen der Einheitsstruktur von der Hartmaskenschicht auf ein Substrat (101) unterhalb der Hartmaskenschicht.

公开(公告)号：CA2843399A1

公开(公告)日：2012-09-27

申请号：CA2843399

申请日：2012-01-30

Applicant: IBM

Inventor： YIN YUNGPENG ,  ARNOLD JOHN C ,  COLBURN MATTHEW E ,  BURNS SEAN D

IPC: H01L21/027

Abstract: An improved method of performing sidewall spacer image transfer is presented. The method includes forming a set of sidewall spacers (109a) next to a plurality of mandrels (106a), the set of sidewall spacers being directly on top of a hard-mask layer (105); transferring image of at least a portion of the set of sidewall spacers to the hard- mask layer to form a device pattern (105a); and transferring the device pattern from the hard- mask layer to a substrate (101) underneath the hard-mask layer.