公开(公告)号：CH613789A5

公开(公告)日：1979-10-15

申请号：CH533077

申请日：1977-04-28

Applicant: IBM

Inventor： BIRNEY RICHARD EUGENE ,  DABIS MICHAEL IAN ,  GRAYBIEL LYNN ALLAN ,  HOOD ROBERT ALLEN ,  KAHN SAMUEL ,  OSBORNE WILLIAM STEESE ,  MCDERMOTT THOMAS STEPHEN ,  WISE LARRY EDWARD

IPC: G06F9/312 ,  G06F12/14 ,  G06F13/12 ,  G06F9/06

Abstract: In the data processing system, one section each (32, 33, 34, 35) of a key register is provided for different types of memory access. A selection circuit (20), the data inputs of which are connected to the key register sections and the control inputs of which are connected to memory access selection signal lines (22, 23, 24, 25) of one or more processors, can be used to select an active memory access key in each case, depending on the type of access. An additional section (31) of the key register is provided for cycle-stealing accesses (memory accesses by a peripheral device without formal program interrupt) and connected to a data input of the selection circuit (20) so that an active memory access key can be selected by means of access signals on a selection signal line (21), connected to another control input of the selection circuit, of an input/output channel mechanism, also including I/O cycle stealing accesses.