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    METHOD AND DEVICE FOR EXTENDED ERROR PROCESSING FOR I/O LOADING/STORING OPERATION ON PCI DEVICE BY ILLEGAL PARITY OR 0-BYTE ENABLING
    3.
    发明专利
    METHOD AND DEVICE FOR EXTENDED ERROR PROCESSING FOR I/O LOADING/STORING OPERATION ON PCI DEVICE BY ILLEGAL PARITY OR 0-BYTE ENABLING 失效

    公开(公告)号：JPH11353244A

    公开(公告)日：1999-12-24

    申请号：JP11065099

    申请日：1999-04-19

    Applicant: IBM

    Inventor： BOSSEN DOUGLAS CRAIG ,  MCLAUGHLIN CHARLES ANDREW ,  DANNY MARVIN NEIL ,  NICHOLSON JAMES OTTO ,  THURBER STEVEN MARK

    IPC: G06F13/00 ,  G06F11/07

    Abstract: PROBLEM TO BE SOLVED: To prevent damage due to a bus error in loading operation or storing operation through the identification of a device which encountered an error before by using forcible illegal data parity or 0-byte enabling. SOLUTION: Device select lines from respective I/O devices 132 and 134 are connected individually to a PCT host bridge 124 and if an error occurs on a PCI(peripheral component interconnect) bus, the device number of the faulty device is recorded in an error register 204. Following loading operation and storing operation are suspended until the error register is reset and until the device number of the object device is checked in the error register. If the object device got out of order before, the completion of the loading/storing operation on the device is stopped by forcing the illegal parity or setting all of byte enabling to zero. The I/O devices activate their device select lines when the illegal parity of 0-byte enabling is forced to answer a load request or store request, but accept no store data.

    METHOD AND SYSTEM FOR SEPARATING FAULT OF PCI BUS ERROR
    4.
    发明专利
    METHOD AND SYSTEM FOR SEPARATING FAULT OF PCI BUS ERROR 失效

    公开(公告)号：JPH113294A

    公开(公告)日：1999-01-06

    申请号：JP7008098

    申请日：1998-03-19

    Applicant: IBM

    Inventor： MCLAUGHLIN CHARLES ANDREW ,  KITAMORN ALONGKORN

    IPC: G06F11/22 ,  G06F11/00 ,  G06F11/267 ,  G06F13/00

    Abstract: PROBLEM TO BE SOLVED: To provide a method and a system for separating a fault on a bus. SOLUTION: This method for separating a fault state on the bus of a computer system provided with an input/output (I/O) sub system 18 formed by plural input/output devices for performing communication through the bus includes repetitive classification of the input/output sub system 18 into a prescribed range and separation of the generation source of an error state inside the input/ output sub system 18. Further, the input/output sub-system 18 performs the communication through a peripheral component interconnection PCI bus 21. In the system, the computer system for separating the fault state on the PCI bus 21 is provided with a processing mechanism and an input/output mechanism connected to the processing mechanism. The input/output mechanism is provided with the plural input/output devices 20 and a bridge connected to the PCI bus 21 for performing the communication corresponding to a PCI standard. Further, this system is provided with a fault separating mechanism for identifying the generation source of the error state in the input/output mechanism inside the processing mechanism.

    METHOD AND SYSTEM FOR ISOLATING FAULTS OF PCI BUS
    5.
    发明专利
    METHOD AND SYSTEM FOR ISOLATING FAULTS OF PCI BUS 未知

    公开(公告)号：CZ346099A3

    公开(公告)日：1999-12-15

    申请号：CZ346099

    申请日：1998-03-23

    Applicant: IBM

    Inventor： MCLAUGHLIN CHARLES ANDREW ,  KITAMORN ALONGKOM

    IPC: G06F11/22 ,  G06F11/00 ,  G06F11/267 ,  G06F13/00

    Abstract: Method and system aspects for fault isolation on a bus are provided. In a method aspect, a method for isolating a fault condition on a bus of a computer system, the computer system including an input/output (I/O) subsystem formed by a plurality of I/O devices communicating via the bus, includes categorizing, in a recursive manner, the I/O subsystem, and isolating a source of an error condition within the I/O subsystem. Further, the I/O subsystem communicates via a peripheral component interconnect, PCI, bus. In a system aspect, a computer system for isolating a fault condition on a PCI bus includes a processing mechanism, and an input/output mechanism, coupled to the processing mechanism, comprising a plurality of input/output devices and bridges coupled to a PCI bus and communicating according to a PCI standard. In addition, the system includes a fault isolation mechanism within the processing mechanism for identifying a source of an error condition in the input/output mechanism. Further, the fault isolation mechanism performs categorization of the input/output mechanism in a recursive manner.

    METHOD OF AND SYSTEM FOR ISOLATING FAULTS FOR PCI BUS ERRORS
    6.
    发明专利
    METHOD OF AND SYSTEM FOR ISOLATING FAULTS FOR PCI BUS ERRORS 未知

    公开(公告)号：PL335938A1

    公开(公告)日：2000-05-22

    申请号：PL33593898

    申请日：1998-03-23

    Applicant: IBM

    Inventor： MCLAUGHLIN CHARLES ANDREW ,  KITAMORN ALONGKORN

    IPC: G06F11/22 ,  G06F11/00 ,  G06F11/267 ,  G06F13/00

    Abstract: Method and system aspects for fault isolation on a bus are provided. In a method aspect, a method for isolating a fault condition on a bus of a computer system, the computer system including an input/output (I/O) subsystem formed by a plurality of I/O devices communicating via the bus, includes categorizing, in a recursive manner, the I/O subsystem, and isolating a source of an error condition within the I/O subsystem. Further, the I/O subsystem communicates via a peripheral component interconnect, PCI, bus. In a system aspect, a computer system for isolating a fault condition on a PCI bus includes a processing mechanism, and an input/output mechanism, coupled to the processing mechanism, comprising a plurality of input/output devices and bridges coupled to a PCI bus and communicating according to a PCI standard. In addition, the system includes a fault isolation mechanism within the processing mechanism for identifying a source of an error condition in the input/output mechanism. Further, the fault isolation mechanism performs categorization of the input/output mechanism in a recursive manner.

    8.
    发明专利
    未知

    公开(公告)号：DE69914966D1

    公开(公告)日：2004-04-01

    申请号：DE69914966

    申请日：1999-04-19

    Applicant: IBM

    Inventor： BOSSEN DOUGLAS CRAIG ,  MCLAUGHLIN CHARLES ANDREW ,  NEAL DANNY MARVIN ,  NICHOLSON JAMES OTTO ,  THURBER STEVEN MARK

    IPC: G06F13/00 ,  G06F11/07 ,  G06F11/00

    Abstract: Device selects lines 202n from each I/O device 132 are brought into a PCI host bridge 124 individually so that the device number of a failing device may be logged in an error register 204 when an error is seen on the PCI bus. Until the error register is reset, subsequent load and store operations are delayed until the device number of the subject device may be checked against the error register. If the subject device is a previously failing device, the load/store operation to that device is prevented from completing, either by forcing bad parity or zeroing all byte enables. By forcing bad parity or zero byte enables, the I/O device will respond to the load or store request by activating its device select line, but will not accept store data. Operations to devices which are not logged in the error register are permitted to proceed normally, as are all load store operations when the error register is clear. Normal system operations are thus not impacted, and operations during error recovery are permitted to proceed if no further damage will be caused by such operations.

    A method and system for fault isolation for pci bus errors
    9.
    发明专利
    A method and system for fault isolation for pci bus errors 未知

    公开(公告)号：SG76539A1

    公开(公告)日：2000-11-21

    申请号：SG1998000475

    申请日：1998-03-02

    Applicant: IBM

    Inventor： MCLAUGHLIN CHARLES ANDREW ,  KITAMORN ALONGKORN

    IPC: G06F11/22 ,  G06F11/00 ,  G06F11/267 ,  G06F13/00

    Abstract: Method and system aspects for fault isolation on a bus are provided. In a method aspect, a method for isolating a fault condition on a bus of a computer system, the computer system including an input/output (I/O) subsystem formed by a plurality of I/O devices communicating via the bus, includes categorizing, in a recursive manner, the I/O subsystem, and isolating a source of an error condition within the I/O subsystem. Further, the I/O subsystem communicates via a peripheral component interconnect, PCI, bus. In a system aspect, a computer system for isolating a fault condition on a PCI bus includes a processing mechanism, and an input/output mechanism, coupled to the processing mechanism, comprising a plurality of input/output devices and bridges coupled to a PCI bus and communicating according to a PCI standard. In addition, the system includes a fault isolation mechanism within the processing mechanism for identifying a source of an error condition in the input/output mechanism. Further, the fault isolation mechanism performs categorization of the input/output mechanism in a recursive manner.

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