公开(公告)号：DE69924179D1

公开(公告)日：2005-04-21

申请号：DE69924179

申请日：1999-04-29

Applicant: IBM

Inventor： DELL TIMOTHY J ,  HEDBERG ERIK L ,  KELLOGG MARK W

IPC: G11C11/407 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C7/00

Abstract: A memory device is provided which stacks commands and internally executes each command at the appropriate time, thereby ensuring contiguous data I/O. The memory device is capable of initiating memory accesses either immediately or "stacking" the command along with a "clock count". The clock count defines the number of clock cycles that must occur prior to execution of the command by the memory device. The memory device initiates memory accesses either immediately, or delayed by the number of clocks defined by the clock count for that command. The memory device operates as a slave to the memory controller and therefore has no ability to execute instructions at a time other than that defined by the memory controller.

公开(公告)号：SG77255A1

公开(公告)日：2000-12-19

申请号：SG1999003392

申请日：1999-07-15

Applicant: IBM

Inventor： BERTIN CLAUDE LOUIS ,  KELLOGG MARK WILLIAM ,  HEDBERG ERIK L ,  DELL TIMOTHY JAY

IPC: G06F13/16 ,  G06F13/38 ,  H01L21/8242

Abstract: A high bandwidth DRAM is provided with two separate bus networks connecting the DRAM to a processor. One bus network is a high speed (e.g., 500 MHZ) 8:1 or 16:1 multiplexed I/O bus and the second is a slower (e.g., 64-bit) bus. The high-speed bus is used for example for graphic intensive applications which require fast access to large numbers of bits in the DRAM memory array. This of course results in higher power requirements. Since, not all applications require such large amounts of data to be transferred between the DRAM and the processor, the slower bus is provided for these less demanding applications such as word processors, spreadsheets, and the like. The slower bus requires less power to operate and therefore results in a power saving mode which, among other things, facilitates longer battery life.

公开(公告)号：MY123248A

公开(公告)日：2006-05-31

申请号：MYPI9904527

申请日：1999-10-20

Applicant: IBM

Inventor： BARTH JOHN E JR ,  BERTIN CLAUDE L ,  DREIBELBIS JEFFREY H ,  ELLIS WAYNE F ,  HOWELL WAYNE J ,  HEDBERG ERIK L ,  KALTER HOWARD LEO ,  TONTI WILLIAM R ,  WHEATER DONALD L

IPC: G11C29/00 ,  H01L21/66 ,  G01R31/28 ,  G01R31/319

Abstract: WAFER TEST AND BURN-IN IS ACCOMPLISHED WITH STATE MACHINE OR PROGRAMMABLE TEST ENGINES (29) LOCATED ON THE WAFER (26) BEING TESTED. EACH TEST ENGINE REQUIRE LESS THAN 10 CONNECTIONS AND EACH TEST ENGINE CAN BE CONNECTED TO A PLURALITY OF CHIPS (28-28", 28A-28E), SUCH AS A ROW OR A COLUMN OF CHIPS ON THE WAFER. THUS, THE NUMBER OF PADS (1-8) OF THE WAFER THAT MUST BE CONNECTED FOR TEST IS SUBSTANTIALLY REDUCED WHILE A LARGE DEGREE OF PARALLEL TESTING IS STILL PROVIDED. THE TEST ENGINES ALSO PERMIT ON-WAFER ALLOCATION OF REDUNDANCY IN PARALLEL SO THAT FAILING CHIPS CAN BE REPAIRED AFTER BURN-IN COMPLETE. IN ADDITION, THE PROGRAMMABLE TEST ENGINES CAN HAVE THEIR CODE ALTERED SO TEST PROGRAMS CAN BE MODIFIED TO ACCOUNT FOR NEW INFORMATION AFTER THE WAFER HAS BEEN FABRICATED. THE TEST ENGINES ARE USED DURING BURN-IN TO PROVIDE HIGH FREQUENCY WRITE SIGNALS TO DRAM ARRAYS THAT PROVIDE A HIGHER EFFECTIVE VOLTAGE TO THE ARRAYS, LOWERING THE TIME REQUIRED FOR BURN-IN. CONNECTIONS TO THE WAFER AND BETWEEN TEST ENGINES AND CHIPS ARE PROVIDED ALONG A MEMBERANE (20-20') ATTACHED TO THE WAFER. MEMBRANE CONNECTORS (31-31") CAN BE FORMED OR OPENED AFTER THE MEMBRANE IS CONNECTED TO THE WAFER SO SHORTED CHIPS CAN BE DISCONNECTED.PREFERABLY THE MEMBRANE REMAINS ON THE WAFER AFTER TEST, BURN-IN AND DICING TO PROVIDE A CHIP SCALE PACKAGE. THUS, THE VERY HIGH COST OF TCE MATCHED MATERIALS, SUCH AS GALSS CERAMIC CONTATCTORS, FOR WAFER BURN-IN IS AVOIDED WHILE PROVIDING BENEFIT BEYOND TEST AND BURN-IN FOR PACKAGING. (FIG. 2)

公开(公告)号：DE69924179T2

公开(公告)日：2006-03-23

申请号：DE69924179

申请日：1999-04-29

Applicant: IBM

Inventor： DELL TIMOTHY J ,  HEDBERG ERIK L ,  KELLOGG MARK W

IPC: G11C7/00 ,  G11C11/407 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401

Abstract: A memory device is provided which stacks commands and internally executes each command at the appropriate time, thereby ensuring contiguous data I/O. The memory device is capable of initiating memory accesses either immediately or "stacking" the command along with a "clock count". The clock count defines the number of clock cycles that must occur prior to execution of the command by the memory device. The memory device initiates memory accesses either immediately, or delayed by the number of clocks defined by the clock count for that command. The memory device operates as a slave to the memory controller and therefore has no ability to execute instructions at a time other than that defined by the memory controller.

公开(公告)号：CA1268519A

公开(公告)日：1990-05-01

申请号：CA546779

申请日：1987-09-14

Applicant: IBM

Inventor： DREIBELBIS JEFFREY H ,  FLAKER ROY C ,  HEDBERG ERIK L

IPC: G05F3/24 ,  G05F1/46 ,  G11C5/14 ,  G11C11/407 ,  H02J3/04 ,  H02M1/00 ,  H02M1/10 ,  H03K19/00

Abstract: Power Supply Adapter Systems A power supply adapter system is provided which includes a voltage supply source terminal, an output terminal, first and second switches, the first switch being disposed between the voltage supply source terminal and the output terminal, voltage conversion means serially connected with the second switch and disposed between the voltage supply source terminal and a point of reference potential and having an output coupled to the output terminal, and means for detecting first and second ranges of voltages at the power supply source terminal and for producing first and second control voltages, respectively, to control the first and second switches. BU9-86-016