公开(公告)号：US3639186A

公开(公告)日：1972-02-01

申请号：US3639186D

申请日：1969-02-24

Applicant: IBM

Inventor： FORSTER THEODOR ,  MOHR THEODOR O

IPC: H01L21/00 ,  H01L21/205 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/316 ,  H01L23/485 ,  H01L29/00 ,  H01L7/50 ,  H01L7/44

CPC classification number: H01L23/485 ,  H01L21/00 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02661 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/3085 ,  H01L21/31662 ,  H01L29/00 ,  H01L2924/0002 ,  Y10S148/106 ,  Y10S148/118 ,  Y10S148/139 ,  Y10S148/143 ,  Y10S438/947 ,  Y10S438/98 ,  H01L2924/00

Abstract: A method for fabricating finely etched patterns is disclosed. The steps include the etching of closely spaced windows in an oxide layer (SiO2) which covers the surface of a semiconductor substrate. The substrate with the exposed semiconductor is then subjected to vapor etching which undercuts the oxide at the interface between the oxide and the semiconductor. The original exposed semiconductor area is enlarged as a result and the spacing between windows narrowed to dimensions not attainable using ordinary photolithographic techniques. By subsequently masking the exposed semiconductor surface with a material which does not dissolve in an etchant for the oxide and etching the oxide, the oxide can be removed forming an exposed region on the semiconductor surface which is extremely narrow. A method for fabricating a Schottky barrier field effect transistor is also disclosed.

Abstract translation: 公开了一种用于制造精细蚀刻图案的方法。 这些步骤包括在覆盖半导体衬底的表面的氧化物层（SiO 2）中蚀刻紧密间隔的窗口。 然后对具有暴露的半导体的衬底进行蒸镀蚀刻，其在氧化物和半导体之间的界面处切割氧化物。 因此，原始暴露的半导体区域被扩大，并且窗口之间的间距变窄到使用普通光刻技术不能达到的尺寸。 通过随后用不溶于氧化物蚀刻剂和蚀刻氧化物的材料掩蔽暴露的半导体表面，可以去除在非常窄的半导体表面上形成暴露区域的氧化物。 还公开了一种用于制造肖特基势垒场效应晶体管的方法。

公开(公告)号：DE1908901A1

公开(公告)日：1969-09-25

申请号：DE1908901

申请日：1969-02-22

Applicant: IBM

Inventor： FORSTER THEODOR ,  OSKAR MOHR THEODOR

IPC: H01L21/00 ,  H01L21/316 ,  H01L23/485 ,  H01L29/00

公开(公告)号：DE69204828D1

公开(公告)日：1995-10-19

申请号：DE69204828

申请日：1992-06-09

Applicant: IBM

Inventor： FORSTER THEODOR ,  HARDER CHRISTOPH DR ,  OOSENBRUG ALBERTUS ,  RUBLOFF GARY W

IPC: H01S5/00 ,  H01S5/02 ,  H01S3/025

Abstract: Method for full-wafer processing of laser diodes with cleaved facets combining the advantages of full-wafer processing, to date known from processing lasers with etched facets, with the advantages of cleaved facets. The basic steps of are: 1. defining the position (17) of the facets (18,19) to be cleaved by scribing marks (13) into the top surface of a laser structure comprising epitaxially grown layers, these scribed marks being perpendicular to the optical axis of the lasers to be made, the scribed marks being parallel, their distance (Ic) defining the lenght of the laser cavities and the distance (Ib) between the facets of neighboring laser diodes; 2. covering the uppermost portion of said layers with an etch mask pattern which covers each laser diode to be made such that it extends over the scribed marks of each laser and provides for etch windows between the scribed marks defining the position of facets of neighboring lasers; 3. etching trenches into an upper portion of said laser structure, the shape and location of said trenches being defined by said etch winddows; 4. partly underetching (16) said upper portion during a second etch step such that said laser facets (18,19) can be defined by cleaving said upper portion along said scribed marks (13) without cleaving the whole laser structure; 5. ultrasonically or mechanically cleaving said upper portions being underetched along said scribed marks providing for facets (18,19) being perpendicular to said layers and the optical axis; 6. separating the laser diodes by cleaving them between neighboring lasers.

公开(公告)号：DE69204828T2

公开(公告)日：1996-05-02

申请号：DE69204828

申请日：1992-06-09

Applicant: IBM

Inventor： FORSTER THEODOR ,  HARDER CHRISTOPH DR ,  OOSENBRUG ALBERTUS ,  RUBLOFF GARY W

IPC: H01S5/00 ,  H01S5/02 ,  H01S3/025

Abstract: Method for full-wafer processing of laser diodes with cleaved facets combining the advantages of full-wafer processing, to date known from processing lasers with etched facets, with the advantages of cleaved facets. The basic steps of are: 1. defining the position (17) of the facets (18,19) to be cleaved by scribing marks (13) into the top surface of a laser structure comprising epitaxially grown layers, these scribed marks being perpendicular to the optical axis of the lasers to be made, the scribed marks being parallel, their distance (Ic) defining the lenght of the laser cavities and the distance (Ib) between the facets of neighboring laser diodes; 2. covering the uppermost portion of said layers with an etch mask pattern which covers each laser diode to be made such that it extends over the scribed marks of each laser and provides for etch windows between the scribed marks defining the position of facets of neighboring lasers; 3. etching trenches into an upper portion of said laser structure, the shape and location of said trenches being defined by said etch winddows; 4. partly underetching (16) said upper portion during a second etch step such that said laser facets (18,19) can be defined by cleaving said upper portion along said scribed marks (13) without cleaving the whole laser structure; 5. ultrasonically or mechanically cleaving said upper portions being underetched along said scribed marks providing for facets (18,19) being perpendicular to said layers and the optical axis; 6. separating the laser diodes by cleaving them between neighboring lasers.

公开(公告)号：DE3475452D1

公开(公告)日：1989-01-05

申请号：DE3475452

申请日：1984-05-30

Applicant: IBM

Inventor： FORSTER THEODOR ,  KERN DIETER ,  VETTIGER PETER ,  WILSON ALAN DIXON

IPC: H01J37/305 ,  G03F7/20 ,  H01J37/317 ,  H01L21/027 ,  H01J37/304

Abstract: Data from a computer are supplied to a pattern generator and represent the shape to be produced. The origin coordinates and incremental steps are signalled to a digital-analog converter. The resulting signals are supplied to the electron beam deflection coils (19,21) following amplification (29). A detector determines a signal representing the rate of electron back-scattering. The signal is amplified and applied to a multi-level range coder. The corresponding level signal is applied to a stepping rate selector which produces a corresponding stepping rate correction which corresponds to the signal level. This is converted to an ac voltage for application to a VCO controlling the beam stepping rate signal for the pattern generator.

公开(公告)号：CA874144A

公开(公告)日：1971-06-22

申请号：CA874144D

Applicant: IBM

Inventor： FORSTER THEODOR ,  MOHR THEODOR O