1.
    发明专利
    未知

    公开(公告)号:DE69204828T2

    公开(公告)日:1996-05-02

    申请号:DE69204828

    申请日:1992-06-09

    Applicant: IBM

    Abstract: Method for full-wafer processing of laser diodes with cleaved facets combining the advantages of full-wafer processing, to date known from processing lasers with etched facets, with the advantages of cleaved facets. The basic steps of are: 1. defining the position (17) of the facets (18,19) to be cleaved by scribing marks (13) into the top surface of a laser structure comprising epitaxially grown layers, these scribed marks being perpendicular to the optical axis of the lasers to be made, the scribed marks being parallel, their distance (Ic) defining the lenght of the laser cavities and the distance (Ib) between the facets of neighboring laser diodes; 2. covering the uppermost portion of said layers with an etch mask pattern which covers each laser diode to be made such that it extends over the scribed marks of each laser and provides for etch windows between the scribed marks defining the position of facets of neighboring lasers; 3. etching trenches into an upper portion of said laser structure, the shape and location of said trenches being defined by said etch winddows; 4. partly underetching (16) said upper portion during a second etch step such that said laser facets (18,19) can be defined by cleaving said upper portion along said scribed marks (13) without cleaving the whole laser structure; 5. ultrasonically or mechanically cleaving said upper portions being underetched along said scribed marks providing for facets (18,19) being perpendicular to said layers and the optical axis; 6. separating the laser diodes by cleaving them between neighboring lasers.

    2.
    发明专利
    未知

    公开(公告)号:DE3576610D1

    公开(公告)日:1990-04-19

    申请号:DE3576610

    申请日:1985-12-06

    Applicant: IBM

    Abstract: A process for the fabrication of "low temperature"-­gate MESFET structures (10), i.e., gate metal (15G) deposition takes place after annealing of the n⁺-implant that form source- (13S) and drain- (13D) contact regions. The process permits self-alignment of all three important MESFET parts, namely the implanted contact regions (13S, 13D) and both, the ohmic- (14S, 14D) as well as the gate- ­(15G) contact metallizations.In the process, a multi-layer "inverted-T" structure (30) is used as a mask for the n⁺-implant and for the ohmic- and gate-metallizations. The upper part (23G) of the "inverted-T" is a so-called dummy gate which is replaced by the Schottky gate after ohmic contact metal deposition. The source-gate and drain-gate separations are determined by the shoulders of the lower layer (22G), the shoulders being obtained using sidewall techniques.

    3.
    发明专利
    未知

    公开(公告)号:DE69006353T2

    公开(公告)日:1994-06-23

    申请号:DE69006353

    申请日:1990-05-25

    Applicant: IBM

    Abstract: A method for cleaving semiconductor wafers, or segments thereof, which comprises placing the wafer (11), provided with scribe lines (15) defining the planes where cleaving is to take place, inbetween a pair of flexible transport bands (12,13) and guiding it around a curved, large radius surface (21) thereby applying a bending moment. With a moment of sufficient magnitude, individual bars (22) are broken off the wafer as this is advanced, the bars having front- and rear-end facets. On cleaving, each bar, while still pressed against the curved surface, is automatically separated whereby mutual damage of the facets of neighbouring bars is prevented. For further handling, e.g. for the transport of the bars to an evaporation station for passivation layer deposition, provisions are made to keep the bars separated. Cleaving and the subsequent passivation coating can be carried out in-situ in a vacuum system to prevent facet contamination prior to applying the passivation.

    4.
    发明专利
    未知

    公开(公告)号:DE69006353D1

    公开(公告)日:1994-03-10

    申请号:DE69006353

    申请日:1990-05-25

    Applicant: IBM

    Abstract: A method for cleaving semiconductor wafers, or segments thereof, which comprises placing the wafer (11), provided with scribe lines (15) defining the planes where cleaving is to take place, inbetween a pair of flexible transport bands (12,13) and guiding it around a curved, large radius surface (21) thereby applying a bending moment. With a moment of sufficient magnitude, individual bars (22) are broken off the wafer as this is advanced, the bars having front- and rear-end facets. On cleaving, each bar, while still pressed against the curved surface, is automatically separated whereby mutual damage of the facets of neighbouring bars is prevented. For further handling, e.g. for the transport of the bars to an evaporation station for passivation layer deposition, provisions are made to keep the bars separated. Cleaving and the subsequent passivation coating can be carried out in-situ in a vacuum system to prevent facet contamination prior to applying the passivation.

    5.
    发明专利
    未知

    公开(公告)号:DE69204828D1

    公开(公告)日:1995-10-19

    申请号:DE69204828

    申请日:1992-06-09

    Applicant: IBM

    Abstract: Method for full-wafer processing of laser diodes with cleaved facets combining the advantages of full-wafer processing, to date known from processing lasers with etched facets, with the advantages of cleaved facets. The basic steps of are: 1. defining the position (17) of the facets (18,19) to be cleaved by scribing marks (13) into the top surface of a laser structure comprising epitaxially grown layers, these scribed marks being perpendicular to the optical axis of the lasers to be made, the scribed marks being parallel, their distance (Ic) defining the lenght of the laser cavities and the distance (Ib) between the facets of neighboring laser diodes; 2. covering the uppermost portion of said layers with an etch mask pattern which covers each laser diode to be made such that it extends over the scribed marks of each laser and provides for etch windows between the scribed marks defining the position of facets of neighboring lasers; 3. etching trenches into an upper portion of said laser structure, the shape and location of said trenches being defined by said etch winddows; 4. partly underetching (16) said upper portion during a second etch step such that said laser facets (18,19) can be defined by cleaving said upper portion along said scribed marks (13) without cleaving the whole laser structure; 5. ultrasonically or mechanically cleaving said upper portions being underetched along said scribed marks providing for facets (18,19) being perpendicular to said layers and the optical axis; 6. separating the laser diodes by cleaving them between neighboring lasers.

    METHOD FOR BATCH CLEAVING SEMICONDUCTOR WAFERS AND FOR COATING THE CLEAVED FACETS

    公开(公告)号:CA2043173C

    公开(公告)日:1993-09-21

    申请号:CA2043173

    申请日:1991-05-24

    Applicant: IBM

    Abstract: A method for cleaving semiconductor wafers, or segments thereof, which comprises placing the wafer (11), provided with scribe lines (15) defining the planes where cleaving is to take place, inbetween a pair of flexible transport bands (12, 13) and guiding it around a curved, large radius surface (21) therebyapplying a bending moment. With a moment of sufficient magnitude, individual bars (22) are broken off the wafer as this is advanced, the bars having frontand rear-end facets. On cleaving, each bar, while still pressed against the curved surface, is automatically separated whereby mutual damage of the facets of neighbouring bars is prevented. For further handling, e.g. for the transport of the bars to an evaporation station for passivation layer deposition, provisions are made to keep the bars separated. Cleaving and the subsequent passivation coating can be carried out in-situ in a vacuum system to prevent facet contamination prior to applying the passivation.

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