公开(公告)号：DE2967090D1

公开(公告)日：1984-08-09

申请号：DE2967090

申请日：1979-11-19

Applicant: IBM

Inventor： GARDINER JAMES ROBERT ,  PLISKIN WILLIAM AARON ,  REVITZ MARTIN ,  SHEPARD JOSEPH FRANCIS

IPC: H01L29/78 ,  H01L21/033 ,  H01L21/28 ,  H01L21/336 ,  H01L29/417 ,  H01L29/778 ,  H01L21/00

Abstract: A method of making a metal-oxide-semiconductor device is disclosed. A thin silicon dioxide insulating layer is formed on the surface of a planar silicon wafer. A first layer of intrinsic polycrystalline silicon is deposited over the dioxide layer, and a second layer of doped polycrystalline silicon is deposited over the intrinsic layer, thereby forming the gate. Subsequent hot processing steps result in diffusion of a portion of the dopant from the doped polycrystalline layer into and throughout the intrinsic layer so as to dope the latter. A metal contact layer is then deposited onto the gate and in superimposed vertical alignment with respect to the thin silicon dioxide insulating layer. The instrinsic nature of the first polycrystalline layer reduces grain growth and void formation in the polycrystalline silicon and thereby prevents the silicon dioxide from being attacked by hydrofluoric acid seeping through voids in the polycrystalline layer during subsequent processing. The yield for the manufacture of devices having thin oxide gates is substantially improved.

公开(公告)号：IT1165429B

公开(公告)日：1987-04-22

申请号：IT2812579

申请日：1979-12-18

Applicant: IBM

Inventor： GARDINER JAMES ROBERT ,  PLISKIN WILLIAM AARON ,  REVITZ MARTIN ,  SHEPARD JOSEPH FRANCIS

IPC: H01L29/78 ,  H01L21/033 ,  H01L21/28 ,  H01L21/336 ,  H01L29/417 ,  H01L29/778 ,  H01L

Abstract: A method of making a metal-oxide-semiconductor device is disclosed. A thin silicon dioxide insulating layer is formed on the surface of a planar silicon wafer. A first layer of intrinsic polycrystalline silicon is deposited over the dioxide layer, and a second layer of doped polycrystalline silicon is deposited over the intrinsic layer, thereby forming the gate. Subsequent hot processing steps result in diffusion of a portion of the dopant from the doped polycrystalline layer into and throughout the intrinsic layer so as to dope the latter. A metal contact layer is then deposited onto the gate and in superimposed vertical alignment with respect to the thin silicon dioxide insulating layer. The instrinsic nature of the first polycrystalline layer reduces grain growth and void formation in the polycrystalline silicon and thereby prevents the silicon dioxide from being attacked by hydrofluoric acid seeping through voids in the polycrystalline layer during subsequent processing. The yield for the manufacture of devices having thin oxide gates is substantially improved.

公开(公告)号：DE3171252D1

公开(公告)日：1985-08-08

申请号：DE3171252

申请日：1981-10-29

Applicant: IBM

Inventor： BARTHOLOMEW ROBERT FORBELL ,  GARBARINO PAUL LOUIS ,  GARDINER JAMES ROBERT ,  REVITZ MARTIN ,  SHEPARD JOSEPH FRANCIS

IPC: H01L21/28 ,  H01L21/285 ,  H01L29/78 ,  H01L21/60

公开(公告)号：DE3165364D1

公开(公告)日：1984-09-13

申请号：DE3165364

申请日：1981-05-12

Applicant: IBM

Inventor： GARDINER JAMES ROBERT ,  MAKAREWICZ STANLEY RICHARD ,  REVITZ MARTIN ,  SHEPARD JOSEPH FRANCIS

IPC: H01L27/10 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/8242 ,  H01L23/532 ,  H01L27/108 ,  H01L29/43 ,  H01L29/78 ,  H01L23/52 ,  H01L21/90

Abstract: In double polysilicon devices direct shorts between overlying polysilicon conductors (3,7) due to a "polysilicon void phenomenon" are prevented by patterning an appropriate etch stop (5) between the conductors.