公开(公告)号：DE2967090D1

公开(公告)日：1984-08-09

申请号：DE2967090

申请日：1979-11-19

Applicant: IBM

Inventor： GARDINER JAMES ROBERT ,  PLISKIN WILLIAM AARON ,  REVITZ MARTIN ,  SHEPARD JOSEPH FRANCIS

IPC: H01L29/78 ,  H01L21/033 ,  H01L21/28 ,  H01L21/336 ,  H01L29/417 ,  H01L29/778 ,  H01L21/00

Abstract: A method of making a metal-oxide-semiconductor device is disclosed. A thin silicon dioxide insulating layer is formed on the surface of a planar silicon wafer. A first layer of intrinsic polycrystalline silicon is deposited over the dioxide layer, and a second layer of doped polycrystalline silicon is deposited over the intrinsic layer, thereby forming the gate. Subsequent hot processing steps result in diffusion of a portion of the dopant from the doped polycrystalline layer into and throughout the intrinsic layer so as to dope the latter. A metal contact layer is then deposited onto the gate and in superimposed vertical alignment with respect to the thin silicon dioxide insulating layer. The instrinsic nature of the first polycrystalline layer reduces grain growth and void formation in the polycrystalline silicon and thereby prevents the silicon dioxide from being attacked by hydrofluoric acid seeping through voids in the polycrystalline layer during subsequent processing. The yield for the manufacture of devices having thin oxide gates is substantially improved.

公开(公告)号：CH597691A5

公开(公告)日：1978-04-14

申请号：CH1320176

申请日：1976-10-19

Applicant: IBM

Inventor： ABOAF JOSEPH ADAM ,  BROADIE ROBERT WALLACE ,  JUNCTION HOPEWELL ,  PLISKIN WILLIAM AARON

IPC: H01L21/76 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/331 ,  H01L21/762 ,  H01L29/73

Abstract: A semiconductor device, such as a transistor, integrated circuit or the like, having a pattern of oxidized and densified porous silicon regions extending onto one of its major surfaces for isolating regions of the semiconductor is manufacturable by a relatively simple process. The process involves forming porous silicon regions in the surface of the semiconductor body such as a silicon wafer, in the areas where dielectric isolation between semiconductor devices is desired. The porous silicon regions are then oxidized at a temperature sufficient to completely oxidize the porous silicon. The oxidiation is such that the oxidized porous silicon extends above the surface of the semiconductor wafer. The oxidized porous silicon regions are then subjected to a temperature higher than the oxidizing temperature utilized in the previous step to cause the densification of the oxidized porous silicon regions. The result of this densification step is the collapse of the porous oxide to a dense structure which is substantially planar with the surface of the semiconductor wafer. This densified silicon dioxide structure has an etch rate which is substantially the same as thermally grown silicon dioxide.

公开(公告)号：DE3279672D1

公开(公告)日：1989-06-08

申请号：DE3279672

申请日：1982-07-23

Applicant: IBM

Inventor： PLISKIN WILLIAM AARON ,  RISEMAN JACOB ,  SHEPARD JOSEPH FRANCIS

IPC: H01L21/70 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L29/73

Abstract: A method is described for forming the recessed dielectric isolation in a silicon substrate. This method involves first forming trenches (16) which are less than 1 micron in depth in areas of one principal surface of the silicon substrate where isolation is desired. Where, for example, an NPN bipolar transistor structure is planned to be formed it is usually necessary to have a P+ region (6) underneath the recessed dielectric isolation to allow full isolation between the various bipolar transistor devices. A PNP transistor uses an N+ region underneath the isolation. Where a field effect transistor is planned a channel stop (30) can be substituted for the P+ region. Under the circumstance of bipolar devices, the P+ region (6) is formed in the substrate (2) prior to the deposition of an epitaxial layer (8) thereover. The trench formation is caused to be formed through the epitaxial layer and into the P+ regions therein. The surface of the trenches (16) are then oxidized in an oxidizing ambient to form a silicon dioxide layer (18) thereon. A glass (20) is deposited over this principal surface. The glass used has a thermal coefficient of expansion that approximates that of silicon and has a softening temperature of less than 1200°C. The structure is then heated to a temperature that allows the flow of the deposited glass on the surface so as to fill the trenches. The glass on the principal surface above the trench can be removed by a reactive ion etching method. Alternatively and preferably, the glass is removed from areas other than the immediate area of the trench by lithography and etching techniques followed by a second heating of the structure to cause the glass flow to result in surface planarization.

公开(公告)号：DE2356975A1

公开(公告)日：1974-07-11

申请号：DE2356975

申请日：1973-11-15

Applicant: IBM

Inventor： LEHMAN HERBERT SAUL ,  PLISKIN WILLIAM AARON ,  VROMEN BENJAMIN HERBERT

IPC: H01L29/78 ,  H01L21/316 ,  H01L29/00 ,  H01L11/14

公开(公告)号：AU2029176A

公开(公告)日：1978-06-15

申请号：AU2029176

申请日：1976-12-06

Applicant: IBM

Inventor： ABOAF JOSEPH ADAM ,  BROADIE ROBERT WALLACE ,  PLISKIN WILLIAM AARON

IPC: H01L21/76 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/331 ,  H01L21/762 ,  H01L29/73 ,  H01L21/82 ,  H01L21/326 ,  H01L27/04 ,  H01L21/22 ,  H01L21/265 ,  H01L21/32 ,  H01L21/20 ,  H01L21/324 ,  H01L29/70

Abstract: A semiconductor device, such as a transistor, integrated circuit or the like, having a pattern of oxidized and densified porous silicon regions extending onto one of its major surfaces for isolating regions of the semiconductor is manufacturable by a relatively simple process. The process involves forming porous silicon regions in the surface of the semiconductor body such as a silicon wafer, in the areas where dielectric isolation between semiconductor devices is desired. The porous silicon regions are then oxidized at a temperature sufficient to completely oxidize the porous silicon. The oxidiation is such that the oxidized porous silicon extends above the surface of the semiconductor wafer. The oxidized porous silicon regions are then subjected to a temperature higher than the oxidizing temperature utilized in the previous step to cause the densification of the oxidized porous silicon regions. The result of this densification step is the collapse of the porous oxide to a dense structure which is substantially planar with the surface of the semiconductor wafer. This densified silicon dioxide structure has an etch rate which is substantially the same as thermally grown silicon dioxide.

公开(公告)号：DE2652294A1

公开(公告)日：1977-10-13

申请号：DE2652294

申请日：1976-11-17

Applicant: IBM

Inventor： ABOAF JOSEPH ADAM ,  BROADIE ROBERT WALLACE ,  PLISKIN WILLIAM AARON

IPC: H01L21/76 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/331 ,  H01L21/762 ,  H01L29/73

Abstract: A semiconductor device, such as a transistor, integrated circuit or the like, having a pattern of oxidized and densified porous silicon regions extending onto one of its major surfaces for isolating regions of the semiconductor is manufacturable by a relatively simple process. The process involves forming porous silicon regions in the surface of the semiconductor body such as a silicon wafer, in the areas where dielectric isolation between semiconductor devices is desired. The porous silicon regions are then oxidized at a temperature sufficient to completely oxidize the porous silicon. The oxidiation is such that the oxidized porous silicon extends above the surface of the semiconductor wafer. The oxidized porous silicon regions are then subjected to a temperature higher than the oxidizing temperature utilized in the previous step to cause the densification of the oxidized porous silicon regions. The result of this densification step is the collapse of the porous oxide to a dense structure which is substantially planar with the surface of the semiconductor wafer. This densified silicon dioxide structure has an etch rate which is substantially the same as thermally grown silicon dioxide.

公开(公告)号：DE1283075B

公开(公告)日：1968-11-14

申请号：DEJ0028302

申请日：1965-06-08

Applicant: IBM

Inventor： PLISKIN WILLIAM AARON

IPC: C03C17/28 ,  H01L23/31

公开(公告)号：DE3676458D1

公开(公告)日：1991-02-07

申请号：DE3676458

申请日：1986-07-29

Applicant: IBM

Inventor： BEYER KLAUS DIETRICH ,  GUTHRIE WILLIAM LESLIE ,  MARKAREWICZ STANLEY RICHARD ,  MENDEL ERIC ,  PATRICK WILLIAM JOHN ,  PERRY KATHLEEN ALICE ,  PLISKIN WILLIAM AARON ,  RISEMAN JACOB ,  SCHIABLE PAUL MARTIN ,  STANDLEY CHARLES LAMBER

IPC: H01L21/3205 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/306 ,  H01L21/60

Abstract: A method is disclosed for producing coplanar metal/insulator films on a substrate according to a chem-mech polishing technique. In one example, a substrate (31) having a patterned insulating layer (32) of dielectric material thereon, is coated with a layer of metal (34). The substrate is then placed in a parallel polisher and the metal is removed elsewhere except in the holes (33) where it is left intact (34a). This is made possible through the use of an improved selective slurry which removes the metal much faster than the dielectric material. The insulating layer may then be used as an automatic etch stop barrier.

公开(公告)号：DE3279998D1

公开(公告)日：1989-11-23

申请号：DE3279998

申请日：1982-07-23

Applicant: IBM

Inventor： CHU WEI-KAN ,  PLISKIN WILLIAM AARON ,  RISEMAN JACOB

IPC: H01L21/76 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/762

Abstract: Deep dielectric isolation zones in a substrate are achieved by forming tenches using reactive ion etching. A glass having a coefficient of thermal expansion closely matching that of the substrate is deposited into the trench to entirely or partially fill the trench. Deposition can be by sedimentation, centrifugation or spin-on techniques. The structure is then fired until the glass particles fuse into a continuous glass layer and final smoothing if necessary can be accomplished.

公开(公告)号：IT1165429B

公开(公告)日：1987-04-22

申请号：IT2812579

申请日：1979-12-18

Applicant: IBM

Inventor： GARDINER JAMES ROBERT ,  PLISKIN WILLIAM AARON ,  REVITZ MARTIN ,  SHEPARD JOSEPH FRANCIS

IPC: H01L29/78 ,  H01L21/033 ,  H01L21/28 ,  H01L21/336 ,  H01L29/417 ,  H01L29/778 ,  H01L

Abstract: A method of making a metal-oxide-semiconductor device is disclosed. A thin silicon dioxide insulating layer is formed on the surface of a planar silicon wafer. A first layer of intrinsic polycrystalline silicon is deposited over the dioxide layer, and a second layer of doped polycrystalline silicon is deposited over the intrinsic layer, thereby forming the gate. Subsequent hot processing steps result in diffusion of a portion of the dopant from the doped polycrystalline layer into and throughout the intrinsic layer so as to dope the latter. A metal contact layer is then deposited onto the gate and in superimposed vertical alignment with respect to the thin silicon dioxide insulating layer. The instrinsic nature of the first polycrystalline layer reduces grain growth and void formation in the polycrystalline silicon and thereby prevents the silicon dioxide from being attacked by hydrofluoric acid seeping through voids in the polycrystalline layer during subsequent processing. The yield for the manufacture of devices having thin oxide gates is substantially improved.