公开(公告)号：JPH10303059A

公开(公告)日：1998-11-13

申请号：JP10894598

申请日：1998-04-20

Applicant: IBM

Inventor： DALAL HORMAZDYAR M ,  GAUDENZI GENE JOSEPH ,  GORRELL REBECCA Y ,  TAKACS MARK A ,  TRAVIS JR KENNETH J

IPC: H01G4/228 ,  H01L25/00

Abstract: PROBLEM TO BE SOLVED: To provide a superior direct capacitor attachment by loading a mask so that the opening of the mask exposes the upper face of a high melting point solder ball, making low melting point metallic layer adhere on the high melting point solder ball and forming a capacitor having a low melting point metallic cap. SOLUTION: The high melting point solder ball (solder ball) 18 is formed on the semiconductor moist pad 16 of the multilayer insulating capacitor 10. The solder moist pad 16 is connected to the inner electrodes 11 of the capacitor 10 through a shorting bar 12. The mask 20 having the opening 26 is loaded on the capacitor 10 having a solder ball assembly 14 and the solder ball 18. The uppermost part of the solder ball 18 is exposed and tin 23 is adhered by a solder evaporator. When the solder ball 18 having a tin cap 23 is reflowed, an eutectic alloy 43 is formed on the uppermost part of the solder ball 18 and it can be joined to the circuit 47 of a substrate constituted of copper foil on an organic carrier card 40.

公开(公告)号：JP2003338517A

公开(公告)日：2003-11-28

申请号：JP2003136494

申请日：2003-05-14

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： COPELAND BRUCE ANTHONY ,  GORRELL REBECCA YUNG ,  TAKACS MARK A ,  TRAVIS JR KENNETH J ,  WANG JUN ,  WIGGINS LOVELL B

IPC: H01L21/60 ,  H01L23/485 ,  H05K3/24 ,  H05K3/34

CPC classification number: H01L24/11 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/0508 ,  H01L2224/05568 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/351 ,  H05K3/244 ,  H05K3/3463 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2224/13099 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a lead-free solder alloy on an electronic substrate.
SOLUTION: A metal stack which comprises a thick nickel barrier layer 16 and a copper layer 18 formed on the nickel barrier layer 16 is evaporated or plated with silver and tin (20). By being heated to a prescribed temperature, the copper, tin, and silver form a lead-less tin-silver-copper alloy 22.
COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：提供一种在电子基板上形成无铅焊料合金的方法。 解决方案：包含形成在镍阻挡层16上的厚镍阻挡层16和铜层18的金属堆叠被银和锡（20）蒸发或镀覆。 通过加热到规定的温度，铜，锡和银形成无铅锡 - 银 - 铜 - 铜合金22.版权所有（C）2004，JPO

公开(公告)号：CA1308817C

公开(公告)日：1992-10-13

申请号：CA593138

申请日：1989-03-08

Applicant: IBM

Inventor： BAISE ARNOLD I ,  CASEY JON A ,  CLARKE DAVID R ,  DIVAKARUNI RENUKA S ,  DUNKEL WERNER E ,  HUMENIK JAMES N ,  KANDETZKE STEVEN M ,  KIRBY DANIEL P ,  KNICKERBOCKER JOHN U ,  MATTS AMY T ,  TAKACS MARK A ,  WIGGINS LOVELL B

IPC: H05K1/03 ,  C04B41/48 ,  C04B41/49 ,  H01L21/48 ,  H01L23/08 ,  H01L23/538 ,  H05K3/40 ,  H01L23/14

Abstract: The cracking experienced during thermal cycling of metal:dielectric semiconductor packages results from a mismatch in thermal co-efficients of expansion. The non-hermeticity associated with such cracking can be addressed by backfilling the permeable cracks with a flexible material. Uniform gaps between the metal and dielectric materials can similarly be filled with flexible materials to provide stress relief, bulk compressibility and strength to the package. Furthermore, a permeable, skeletal dielectric can be fabricated as a fired, multilayer structure having sintered metallurgy and subsequently infused with a flexible, temperature-stable material to provide hermeticity and strength. FI9-86-046

公开(公告)号：CA1233914A

公开(公告)日：1988-03-08

申请号：CA503286

申请日：1986-03-04

Applicant: IBM

Inventor： CSERVAK NANCY R ,  FRIBLEY SUSAN K ,  GOTH GEORGE R ,  TAKACS MARK A

IPC: H01L21/76 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/31 ,  H01L21/312 ,  H01L21/762 ,  H01L21/46

Abstract: Disclosed is a process for planarization of semiconductor structures having dielectric isolation regions. Specifically, the process is directed to planarization of an organic polyimide layer obtained following filling of deep trenches in a semiconductor substrate having high and low density trench regions with this material. After over-filling the trenches with the polyimide and obtaining a non-planar polyimide layer having a thickness much larger in the low trench density regions than that in the high density regions, a photoresist layer is applied thereover. The photoresist is then controllably exposed using a mask which is the complement or inverse of the mask used for imaging the trench patterns to obtain a thick blockout photoresist mask over the trenches and a thin wetting layer of photoresist over the remainder of the substrate. Next, by means of a thermal step, the blockout photoresist is caused to reflow to form a relatively thick photoresist layer over the high trench density regions and a thin photoresist layer over the low trench density regions, thereby exactly compensating for the non-planarity of the polyimide layer.