公开(公告)号：SG104319A1

公开(公告)日：2004-06-21

申请号：SG200202503

申请日：2002-04-25

Applicant: IBM

Inventor： FARIBORZ ASSADERAGHI ,  TZE-CHIANG CHEN ,  K PAUL MILLER ,  EDWARD JOSEPH NOWAK ,  GHAVAM G SHAHIDI

IPC: H01L21/336 ,  H01L21/28 ,  H01L29/41 ,  H01L29/78 ,  H01L29/786 ,  H01L21/84

Abstract: Short channel effects are effectively suppressed by steep impurity concentration gradients which can be placed with improved accuracy of location and geometry while relaxing process tolerances by implanting impurities in a polysilicon seed adjacent a conduction channel of a transistor and diffusing impurities therefrom into the conduction channel. The polysilicon seed also allows the epitaxial growth of polysilicon source/drain contacts therefrom having a configuration which minimizes current density and path length therein while providing further mechanical advantages.

公开(公告)号：GB2538896A

公开(公告)日：2016-11-30

申请号：GB201613996

申请日：2015-01-20

Applicant: IBM

Inventor： BAHMAN HEKMATSHOARTABARI ,  GHAVAM G SHAHIDI

IPC: H01L27/06 ,  H01L27/098 ,  H01L29/10 ,  H01L29/808 ,  H01L29/812

Abstract: A junction field-effect transistor (JFET) with a gate region that includes two separate subregions having material of different conductivity types and/or a Schottky junction that substantially suppresses gate current when the gate junction is forward-biased, as well as complementary circuits that incorporate such JFET devices. According to an aspect of the present invention, there is a junction field effect transistor (JFET) that includes a channel region and a gate region. The gate region includes a first gate sub-region and a second gate sub-region. The first gate sub-region forms a junction with the channel region. The second gate sub-region forms a junction with the first gate sub-region. The channel region and the second gate sub-region include material of a first conductivity type. The first gate sub-region includes material of a second conductivity type different from the first conductivity type.

公开(公告)号：SG115598A1

公开(公告)日：2005-10-28

申请号：SG200307829

申请日：2003-12-26

Applicant: IBM

Inventor： HEEMYONG PARK ,  BYOUNG H LEE ,  PAUL D AGNELLO ,  DOMINIC J SCHEPIS ,  GHAVAM G SHAHIDI

IPC: H01L21/00 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L21/28 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/74 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

Abstract: A method and structure for a CMOS device comprises depositing a silicon over insulator (SOI) wafer over a buried oxide (BOX) substrate, wherein the SOI wafer has a predetermined thickness; forming a gate dielectric over the SOI wafer, forming a shallow trench isolation (STI) region over the BOX substrate, wherein the STI region is configured to have a generally rounded corner; forming a gate structure over the gate dielectric; depositing an implant layer over the SOI wafer; performing one of N-type and P-type dopant implantations in the SOI wafer and the implant layer; and hearing the device to form source and drain regions from the implant layer and the SOI wafer, wherein the source and drain regions have a thickness greater than the predetermined thickness of the SOI wafer, wherein the gate dielectric is positioned lower than the STI region.

公开(公告)号：GB2538896B

公开(公告)日：2019-06-05

申请号：GB201613996

申请日：2015-01-20

Applicant: IBM

Inventor： BAHMAN HEKMATSHOARTABARI ,  GHAVAM G SHAHIDI

IPC: H01L27/06 ,  H01L27/098 ,  H01L29/10 ,  H01L29/423 ,  H01L29/808 ,  H01L29/812

公开(公告)号：SG85156A1

公开(公告)日：2001-12-19

申请号：SG1999006334

申请日：1999-12-10

Applicant: IBM

Inventor： ATUL AJMERA ,  EFFENDI LEOBANDUNG ,  WERNER RAUSCH ,  DOMINIC J SCHEPIS ,  GHAVAM G SHAHIDI

IPC: H01L27/12 ,  H01L21/74 ,  H01L21/76 ,  H01L21/762 ,  H01L23/52 ,  H01L23/58 ,  H01L29/786

Abstract: A method for forming a substrate contact in a substrate that includes a silicon on insulator region. A shallow isolation trench is formed in the silicon on insulator substrate. The shallow isolation trench is filled. Photoresist is deposited on the substrate. A contact trench is formed in the substrate through the filled shallow isolation trench, silicon on insulator, and silicon substrate underlying the silicon on insulator region. The contact trench is filled, wherein the material filling the contact trench forms a contact to the silicon substrate.