公开(公告)号：SG104319A1

公开(公告)日：2004-06-21

申请号：SG200202503

申请日：2002-04-25

Applicant: IBM

Inventor： FARIBORZ ASSADERAGHI ,  TZE-CHIANG CHEN ,  K PAUL MILLER ,  EDWARD JOSEPH NOWAK ,  GHAVAM G SHAHIDI

IPC: H01L21/336 ,  H01L21/28 ,  H01L29/41 ,  H01L29/78 ,  H01L29/786 ,  H01L21/84

Abstract: Short channel effects are effectively suppressed by steep impurity concentration gradients which can be placed with improved accuracy of location and geometry while relaxing process tolerances by implanting impurities in a polysilicon seed adjacent a conduction channel of a transistor and diffusing impurities therefrom into the conduction channel. The polysilicon seed also allows the epitaxial growth of polysilicon source/drain contacts therefrom having a configuration which minimizes current density and path length therein while providing further mechanical advantages.

公开(公告)号：MY116040A

公开(公告)日：2003-10-31

申请号：MYPI19993047

申请日：1999-07-20

Applicant: IBM

Inventor： FARIBORZ ASSADERAGHI ,  CLAUDE L BERTIN ,  JEFFREY P GAMBINO ,  LOUIS LU-CHEN HSU ,  JACK ALLAN MANDELMAN

IPC: H01L21/8242 ,  H01L21/336 ,  H01L21/84 ,  H01L27/108 ,  H01L23/52 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

Abstract: AN ACTIVE FET BODY DEVICE WHICH COMPRISES AN ACTIVE FET REGION INCLUDING A GATE (13, 15, 16,24,26,28,30,3 I), A BODY REGION (4) AND ELECTRICAL CONNECTION BETWEEN SAID GATE AND SAID BODY REGION THAT IS LOCATED WITHIN THE ACTIVE FET REGION IS PROVIDED ALONG WITH VARIOUS METHODS FOR FABRICATING THE DEVICES. THE ELECTRICAL CONNECTION EXTENDS OVER SUBSTANTIALLY THE ENTIRE WIDTH OF THE FET. (FIGURE 6)