公开(公告)号：GB2582468A

公开(公告)日：2020-09-23

申请号：GB202007398

申请日：2018-10-22

Applicant: IBM

Inventor： EFFENDI LEOBANDUNG

IPC: H01L29/78

Abstract: A semiconductor device includes a source region and a drain region formed in a transistor structure. A channel region is disposed between the source region and the drain region. A cladding layer is formed on the channel region, the cladding layer including a semiconductor material. A gate dielectric of a gate structure is formed on the cladding layer.

公开(公告)号：GB2538594A

公开(公告)日：2016-11-23

申请号：GB201604088

申请日：2016-03-10

Applicant: IBM

Inventor： NING LI ,  DEVENDRA SADANA ,  EFFENDI LEOBANDUNG

IPC: H01L21/8258 ,  B82Y20/00 ,  G02B6/12 ,  G02B6/13 ,  H01L21/70 ,  H01L27/04 ,  H01L27/15 ,  H01L31/0304 ,  H01L31/18 ,  H01S5/026

Abstract: A method of forming a III-V optoelectronic device 115 and a Si CMOS device on a single chip may include forming a silicon substrate in both a first and second region 101, 103 of a single chip; forming a germanium layer 106 above the substrate in at least the first region; forming the optoelectronic device 115 on the germanium layer in the first region, and forming the silicon device 112 on a silicon layer in the second region 103. The optoelectronic device includes a bottom cladding layer 116, an active region 118 which is adjacent a waveguide 114 and a top cladding layer 117, each layer formed consecutively upon the germanium layer. In one embodiment, a semiconductor layer (206; Fig. 10) is formed on the substrate in first and second regions; a first insulator layer (204; Fig. 10) is formed over the semiconductor layer; a waveguide (214; Fig. 10) is formed over the first insulator layer; and a second insulator layer (208; Fig. 10) is formed over the waveguide. Semiconductor devices (212) are formed upon a base layer (210) over the second insulating layer and the waveguide in the second region, and an optoelectronic device (215; Fig. 10) is formed on the semiconductor layer (206; Fig. 10) in the first region.

公开(公告)号：SG85156A1

公开(公告)日：2001-12-19

申请号：SG1999006334

申请日：1999-12-10

Applicant: IBM

Inventor： ATUL AJMERA ,  EFFENDI LEOBANDUNG ,  WERNER RAUSCH ,  DOMINIC J SCHEPIS ,  GHAVAM G SHAHIDI

IPC: H01L27/12 ,  H01L21/74 ,  H01L21/76 ,  H01L21/762 ,  H01L23/52 ,  H01L23/58 ,  H01L29/786

Abstract: A method for forming a substrate contact in a substrate that includes a silicon on insulator region. A shallow isolation trench is formed in the silicon on insulator substrate. The shallow isolation trench is filled. Photoresist is deposited on the substrate. A contact trench is formed in the substrate through the filled shallow isolation trench, silicon on insulator, and silicon substrate underlying the silicon on insulator region. The contact trench is filled, wherein the material filling the contact trench forms a contact to the silicon substrate.

公开(公告)号：GB2582468B

公开(公告)日：2021-11-03

申请号：GB202007398

申请日：2018-10-22

Applicant: IBM

Inventor： EFFENDI LEOBANDUNG

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/10 ,  H01L29/36 ,  H01L29/66

Abstract: A semiconductor device includes a source region and a drain region formed in a transistor structure. A channel region is disposed between the source region and the drain region. A cladding layer is formed on the channel region, the cladding layer including a semiconductor material. A gate dielectric of a gate structure is formed on the cladding layer.

公开(公告)号：GB2538348A

公开(公告)日：2016-11-16

申请号：GB201604084

申请日：2016-03-10

Applicant: IBM

Inventor： JIN CAI ,  NING LI ,  JEAN-OLIVIER PLOUCHART ,  DEVENDRA SADANA ,  TAK HUNG NING ,  EFFENDI LEOBANDUNG

IPC: H01S5/026 ,  G02B6/42 ,  G02B6/43 ,  H01L27/15

Abstract: After forming a first trench extending through a top semiconductor layer and a buried insulator layer and into a handle substrate 10 of a semiconductor-on-insulator (SOI substrate 8, a dielectric waveguide material stack 22, 24, 26 including a lower dielectric cladding layer, a core layer and an upper dielectric cladding layer is formed within the first trench. Next, at least one lateral bipolar junction transistor (BJT), which can be a PNP BJT 30, an NPN BJT 40 or a pair of complementary PNP BJT 30 and NPN BJT 40, is formed in a remaining portion of the top semiconductor layer. After forming a second trench extending through the dielectric waveguide material stack to re-expose a portion of a bottom surface of the first trench, a laser diode is formed in the second trench. An optoelectronic device, for example a laser diode 60 may be formed on top of the compound semiconductor buffer layer 58 and edge coupled to the dielectric waveguide 22, 24, 26.

公开(公告)号：GB2538348B

公开(公告)日：2019-06-05

申请号：GB201604084

申请日：2016-03-10

Applicant: IBM

Inventor： JIN CAI ,  NING LI ,  JEAN-OLIVIER PLOUCHART ,  DEVENDRA SADANA ,  TAK HUNG NING ,  EFFENDI LEOBANDUNG

IPC: H01S5/026 ,  G02B6/42 ,  G02B6/43 ,  H01L27/15

Abstract: After forming a first trench extending through a top semiconductor layer and a buried insulator layer and into a handle substrate of a semiconductor-on-insulator (SOI) substrate, a dielectric waveguide material stack including a lower dielectric cladding layer, a core layer and an upper dielectric cladding layer is formed within the first trench. Next, at least one lateral bipolar junction transistor (BJT), which can be a PNP BJT, an NPN BJT or a pair of complementary PNP BJT and NPN BJT, is formed in a remaining portion of the top semiconductor layer. After forming a second trench extending through the dielectric waveguide material stack to re-expose a portion of a bottom surface of the first trench, a laser diode is formed in the second trench.

公开(公告)号：GB2538594B

公开(公告)日：2017-11-22

申请号：GB201604088

申请日：2016-03-10

Applicant: IBM

Inventor： NING LI ,  DEVENDRA SADANA ,  EFFENDI LEOBANDUNG

IPC: H01L27/144 ,  B82Y20/00 ,  G02B6/12 ,  G02B6/13 ,  H01L21/70 ,  H01L21/84 ,  H01L25/16 ,  H01L27/04 ,  H01L27/092 ,  H01L27/15 ,  H01L31/0304 ,  H01L31/18 ,  H01S5/02 ,  H01S5/026

Abstract: A single chip including an optoelectronic device on the semiconductor layer in a first region, the optoelectronic device comprises a bottom cladding layer, an active region, and a top cladding layer, wherein the bottom cladding layer is above and in direct contact with the semiconductor layer, the active region is above and in direct contact with the bottom cladding layer, and the top cladding layer is above and in direct contact with the active region, a silicon device on the substrate extension layer in a second region, a device insulator layer substantially covering both the optoelectronic device in the first region and the silicon device in the second region, and a waveguide embedded within the device insulator layer in direct contact with a sidewall of the active region of the optoelectronic device.