公开(公告)号：EP1665334A4

公开(公告)日：2011-02-23

申请号：EP04756338

申请日：2004-06-29

Applicant: IBM

Inventor： PARK HEEMYOUNG ,  AGNELLO PAUL D ,  GILBERT PERCY V ,  LEE BYOUNG H ,  O'NEIL PATRICIA A ,  SHAHIDI GHAVAM G ,  WELSER JEFFREY J

IPC: H01L21/8234 ,  H01L21/336 ,  H01L21/425 ,  H01L21/4763 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/66772 ,  H01L21/84 ,  H01L29/458 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/78621

公开(公告)号：JP2004146824A

公开(公告)日：2004-05-20

申请号：JP2003347653

申请日：2003-10-06

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： FUNG KA HING ,  GILBERT PERCY V

IPC: H01L29/41 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L21/823864 ,  Y10S257/90

Abstract: PROBLEM TO BE SOLVED: To optimize the performance of at least two different field effect transistors that share the same semiconductor substrate.
SOLUTION: At least two field effect transistors 100, 110 are formed on the same substrate 10. The first field effect transistor is provided with a spacer 120 with the first width, and the second field effect transistor is provided with a spacer 130 with the second width, where the first width is different from the second width. By doing this, the spacer width and the transistor performance of the two field effect transistors on the same substrate can be optimized.
COPYRIGHT: (C)2004,JPO

公开(公告)号：WO2005024899A3

公开(公告)日：2008-11-20

申请号：PCT/US2004020850

申请日：2004-06-29

Applicant: IBM ,  PARK HEEMYOUNG ,  AGNELLO PAUL D ,  GILBERT PERCY V ,  LEE BYOUNG H ,  O'NEIL PATRICIA A ,  SHAHIDI GHAVAM G ,  WELSER JEFFREY J

Inventor： PARK HEEMYOUNG ,  AGNELLO PAUL D ,  GILBERT PERCY V ,  LEE BYOUNG H ,  O'NEIL PATRICIA A ,  SHAHIDI GHAVAM G ,  WELSER JEFFREY J

IPC: H01L21/8234 ,  H01L21/336 ,  H01L21/425 ,  H01L21/4763 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/66772 ,  H01L21/84 ,  H01L29/458 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/78621

Abstract: Disclosed is a method and system of forming an integrated circuit transistor having a reduced gate height. The method forms a laminated structure having a substrate, a gate conductor (13) above the substrate, and at least one sacrificial layer (14-16) above the gate conductor (13). The process patterns the laminated structure into at least one gate stack extending from the substrate, forms spacers (60) adjacent to the gate stack, dopes regions of the substrate not protected by the spacers to form source and drain regions (71) adjacent the gate stack, and removes the spacers (60) and the sacrificial layer (14-16).

Abstract translation: 公开了一种形成栅极高度降低的集成电路晶体管的方法和系统。 该方法形成具有衬底，在衬底上方的栅极导体（13）和栅极导体（13）上方的至少一个牺牲层（14-16）的叠层结构。 该过程将层叠结构图案化为从衬底延伸的至少一个栅极堆叠，与栅极叠层相邻形成间隔物（60），不会由间隔物掺杂衬底的区域，以形成邻近栅极的源区和漏区（71） 并且移除间隔物（60）和牺牲层（14-16）。

公开(公告)号：JP2005123597A

公开(公告)日：2005-05-12

申请号：JP2004271982

申请日：2004-09-17

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： AJMERA ATUL C ,  BRYANT ANDRES ,  GILBERT PERCY V ,  GRIBELYUK MICHAEL A ,  MACIEJEWSKI EDWARD P ,  MO RENEE T ,  NARASIMHA SHREESH

IPC: H01L21/28 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/8238 ,  H01L23/52 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L21/02063 ,  H01L21/31116 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a gate electrode that avoids dielectric layer undercut during a silicide precleaning step. SOLUTION: A patterned gate stack includes a gate dielectric below a conductor having vertical sidewalls, and a dielectric layer is formed over the patterned gate stack and substrate surfaces. Nitride spacers are formed overlying the dielectric layer at each vertical sidewall. The dielectric layer on the substrate surface is removed using an etch process such that a portion of the dielectric layer underlying each spacer remains. Then, a nitride layer is deposited over the entire sample and subsequently removed by an etch process such that only a portion of the nitride film ("plug") remains. The plug seals and encapsulates the dielectric layer underlying the each spacer, thus preventing the dielectric material from being undercut during the subsequent silicide precleaning process. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种在硅化物预清洗步骤期间形成避免电介质层底切的栅电极的方法。 解决方案：图案化栅极堆叠包括在具有垂直侧壁的导体下方的栅极电介质，并且在图案化的栅极堆叠和衬底表面上形成介电层。 在每个垂直侧壁处形成覆盖电介质层的氮化物间隔物。 使用蚀刻工艺去除衬底表面上的电介质层，使得每个间隔物下面的电介质层的一部分保留。 然后，在整个样品上沉积氮化物层，然后通过蚀刻工艺去除，使得只有一部分氮化膜（“插塞”）保留。 塞子密封并封装每个间隔物下面的电介质层，从而防止在随后的硅化物预清洗过程中电介质材料被切下。 版权所有（C）2005，JPO＆NCIPI