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    4f-square memory cell having vertical floating- gate transistors with self-aligned shallow trench isolation
    3.
    发明专利
    4f-square memory cell having vertical floating- gate transistors with self-aligned shallow trench isolation 未知

    公开(公告)号：SG60174A1

    公开(公告)日：1999-02-22

    申请号：SG1997004574

    申请日：1997-12-19

    Applicant: IBM

    Inventor： BURNS STUART MCALLISTER JR ,  HANAEL HUSSEIN IBRAHIM ,  KOCON WALDEMAR WALTER ,  WELSER JEFFREY J

    IPC: H01L21/8242 ,  H01L21/8247 ,  H01L27/108 ,  H01L27/115 ,  H01L29/423 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L27/105

    Abstract: A densely packed array of vertical semiconductor devices and methods of making thereof are disclosed. The array has columns of bitlines and rows of wordlines. The gates of the transistors act as the wordlines, while the source or drain regions acts as the bitlines. The array also has vertical pillars, acting as a channel, formed between source and drain regions. The source regions are self-aligned and located below the pillars. The source regions of adjacent bitlines are isolated from each other without increasing the cell size and allowing a minimum area of approximately 4F2 to be maintained. The isolated sources allow individual cells to be addressed and written via direct tunneling, in both volatile and non-volatile memory cell configurations. The source may be initially implanted. Alternatively, the source may be diffused below the pillars after forming thereof. In this case, the source diffusion may be controlled either to form floating pillars isolated from the underlying substrate, or to maintain contact between the pillars and the substrate.

    SELF- ALIGNED DIFFUSED SOURCE VERTICAL TRANSISTORS WITH STACK CAPACITORS IN A 4F- SQUARE MEMORY CELL ARRAY
    4.
    发明专利
    SELF- ALIGNED DIFFUSED SOURCE VERTICAL TRANSISTORS WITH STACK CAPACITORS IN A 4F- SQUARE MEMORY CELL ARRAY 未知

    公开(公告)号：MY118306A

    公开(公告)日：2004-09-30

    申请号：MYPI9706162

    申请日：1997-12-18

    Applicant: IBM

    Inventor： BURNS STUART MCALLISTER JR ,  HANAFI HUSSEIN IBRAHIM ,  KALTER HOWARD LEO ,  KOCON WALDEMAR WALTER ,  WELSER JEFFREY J

    IPC: H01L21/336 ,  H01L21/8238 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/108 ,  H01L27/115 ,  H01L29/76 ,  H01L29/788 ,  H01L29/792

    Abstract: A DENSELY PACKED ARRAY (200, 420, 500, 510, 540, 850) OF VERTICAL SEMICONDUCTOR DEVICES, HAVING PILLARS (230) WITH STACK CAPACITORS (520, 520'') THEREON, AND METHODS OF MAKING THEREOF ARE DISCLOSED. THE PILLARS ACT AS TRANSISTOR CHANNELS, AND ARE FORMED BETWEEN UPPER AND LOWER DOPED REGIONS (240, 405). THE LOWER DOPED REGIONS ARE SELF-ALIGNED AND ARE LOCATED BELOW THE PILLARS. THE ARRAY HAS COLUMNS OF BITLINES (220,700, 705) AND ROWS OF WORD LINES (225, 225''). THE LOWER DOPED REGIONS OF ADJACENT BITLINES MAY BE ISOLATED FROM EACH OTHER WITHOUT INCREASING THE CELL SIZE AND ALLOWING A MINIMUM AREA OF APPROXIMATELY 4F2 TO BE MAINTAINED. THE ARRAY IS SUITABLE FOR GBIT DRAM APPLICATIONS BECAUSE THE STACK CAPACITORS DO NOT INCREASE ARRAY AREA. THE ARRAY MAY HAVE AN OPEN BITLINE, A FOLDED, OR AN OPEN/FOLDED ARCHITECTURE WITH DUAL WORDLINES, WHERE TWO TRANSISTORS ARE FORMED ON TOP OF EACH OTHER IN EACH TRENCH. THE LOWER REGIONS MAY BE INITIALLY IMPLANTED. ALTERNATIVE1Y, THE LOWER REGIONS MAY BE DIFFUSED BELOW THE PILLARS AFTER FORMING THEREOF. IN THIS CASE, THE LOWER REGION DIFFUSION MAY BE CONTROLLED EITHER TO FORM FLOATING PILLARS ISOLATED FROM THE UNDERLYING SUBSTRATE, OR TO MAINTAIN CONTACT BETWEEN THE PILLARS AND THE SUBSTRATE. (FIG.8)

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