公开(公告)号：EP1665334A4

公开(公告)日：2011-02-23

申请号：EP04756338

申请日：2004-06-29

Applicant: IBM

Inventor： PARK HEEMYOUNG ,  AGNELLO PAUL D ,  GILBERT PERCY V ,  LEE BYOUNG H ,  O'NEIL PATRICIA A ,  SHAHIDI GHAVAM G ,  WELSER JEFFREY J

IPC: H01L21/8234 ,  H01L21/336 ,  H01L21/425 ,  H01L21/4763 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/66772 ,  H01L21/84 ,  H01L29/458 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/78621

公开(公告)号：WO2005024899A3

公开(公告)日：2008-11-20

申请号：PCT/US2004020850

申请日：2004-06-29

Applicant: IBM ,  PARK HEEMYOUNG ,  AGNELLO PAUL D ,  GILBERT PERCY V ,  LEE BYOUNG H ,  O'NEIL PATRICIA A ,  SHAHIDI GHAVAM G ,  WELSER JEFFREY J

Inventor： PARK HEEMYOUNG ,  AGNELLO PAUL D ,  GILBERT PERCY V ,  LEE BYOUNG H ,  O'NEIL PATRICIA A ,  SHAHIDI GHAVAM G ,  WELSER JEFFREY J

IPC: H01L21/8234 ,  H01L21/336 ,  H01L21/425 ,  H01L21/4763 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/66772 ,  H01L21/84 ,  H01L29/458 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/78621

Abstract: Disclosed is a method and system of forming an integrated circuit transistor having a reduced gate height. The method forms a laminated structure having a substrate, a gate conductor (13) above the substrate, and at least one sacrificial layer (14-16) above the gate conductor (13). The process patterns the laminated structure into at least one gate stack extending from the substrate, forms spacers (60) adjacent to the gate stack, dopes regions of the substrate not protected by the spacers to form source and drain regions (71) adjacent the gate stack, and removes the spacers (60) and the sacrificial layer (14-16).

Abstract translation: 公开了一种形成栅极高度降低的集成电路晶体管的方法和系统。 该方法形成具有衬底，在衬底上方的栅极导体（13）和栅极导体（13）上方的至少一个牺牲层（14-16）的叠层结构。 该过程将层叠结构图案化为从衬底延伸的至少一个栅极堆叠，与栅极叠层相邻形成间隔物（60），不会由间隔物掺杂衬底的区域，以形成邻近栅极的源区和漏区（71） 并且移除间隔物（60）和牺牲层（14-16）。