公开(公告)号：EP1665334A4

公开(公告)日：2011-02-23

申请号：EP04756338

申请日：2004-06-29

Applicant: IBM

Inventor： PARK HEEMYOUNG ,  AGNELLO PAUL D ,  GILBERT PERCY V ,  LEE BYOUNG H ,  O'NEIL PATRICIA A ,  SHAHIDI GHAVAM G ,  WELSER JEFFREY J

IPC: H01L21/8234 ,  H01L21/336 ,  H01L21/425 ,  H01L21/4763 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/66772 ,  H01L21/84 ,  H01L29/458 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/78621

公开(公告)号：JP2010079896A

公开(公告)日：2010-04-08

申请号：JP2009209893

申请日：2009-09-11

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： XIANG HUA ,  ECONOMIKOS LAERTIS ,  FAYAZ MOHAMMED FAZIL ,  GRECO STEPHEN EDWARD ,  O'NEIL PATRICIA A ,  PURI RUCHIR

IPC: G06F17/50 ,  H01L21/82

CPC classification number: G06F17/5009 ,  G06F2217/12 ,  Y02P90/265

Abstract: PROBLEM TO BE SOLVED: To provide a method, apparatus and computer program for performing simulation of influence of a manufacturing process to electrical performance in the integrated circuit during design stage.
SOLUTION: Methods, apparatus and computer program provide a fast and accurate model for simulating the effects of chemical mechanical polishing (CMP) steps during fabrication of an integrated circuit by generating a design of an integrated circuit, using a simplified model while generating the design of the integrated circuit, predicting at least one physical characteristic of the integrated circuit which results from a processing step to be used during manufacture of the integrated circuit, wherein the simplified model is derived from simulations performed prior to the design generation activities using a comprehensive simulation program used to model the physical characteristic; predicting performance of the integrated circuit using the predicted physical characteristic; and adjusting the design of the integrated circuit in dependence on the performance prediction.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于在设计阶段期间对集成电路中的制造过程对电气性能的影响进行模拟的方法，装置和计算机程序。 解决方案：方法，设备和计算机程序提供了一种快速准确的模型，用于在集成电路制造过程中模拟化学机械抛光（CMP）步骤的效果，通过使用简化模型生成集成电路的设计，同时产生 集成电路的设计，预测由在集成电路的制造期间使用的处理步骤产生的集成电路的至少一个物理特性，其中简化模型是从使用 综合仿真程序用于建模物理特性; 使用预测的物理特性预测集成电路的性能; 并根据性能预测调整集成电路的设计。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：WO2005024899A3

公开(公告)日：2008-11-20

申请号：PCT/US2004020850

申请日：2004-06-29

Applicant: IBM ,  PARK HEEMYOUNG ,  AGNELLO PAUL D ,  GILBERT PERCY V ,  LEE BYOUNG H ,  O'NEIL PATRICIA A ,  SHAHIDI GHAVAM G ,  WELSER JEFFREY J

Inventor： PARK HEEMYOUNG ,  AGNELLO PAUL D ,  GILBERT PERCY V ,  LEE BYOUNG H ,  O'NEIL PATRICIA A ,  SHAHIDI GHAVAM G ,  WELSER JEFFREY J

IPC: H01L21/8234 ,  H01L21/336 ,  H01L21/425 ,  H01L21/4763 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/66772 ,  H01L21/84 ,  H01L29/458 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/78621

Abstract: Disclosed is a method and system of forming an integrated circuit transistor having a reduced gate height. The method forms a laminated structure having a substrate, a gate conductor (13) above the substrate, and at least one sacrificial layer (14-16) above the gate conductor (13). The process patterns the laminated structure into at least one gate stack extending from the substrate, forms spacers (60) adjacent to the gate stack, dopes regions of the substrate not protected by the spacers to form source and drain regions (71) adjacent the gate stack, and removes the spacers (60) and the sacrificial layer (14-16).

Abstract translation: 公开了一种形成栅极高度降低的集成电路晶体管的方法和系统。 该方法形成具有衬底，在衬底上方的栅极导体（13）和栅极导体（13）上方的至少一个牺牲层（14-16）的叠层结构。 该过程将层叠结构图案化为从衬底延伸的至少一个栅极堆叠，与栅极叠层相邻形成间隔物（60），不会由间隔物掺杂衬底的区域，以形成邻近栅极的源区和漏区（71） 并且移除间隔物（60）和牺牲层（14-16）。