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    HETERO-JUNCTION BIPOLAR TRANSISTOR AND ITS MANUFACTURING METHOD
    1.
    发明专利
    HETERO-JUNCTION BIPOLAR TRANSISTOR AND ITS MANUFACTURING METHOD 审中-公开

    公开(公告)号：JP2002329725A

    公开(公告)日：2002-11-15

    申请号：JP2002104250

    申请日：2002-04-05

    Applicant: IBM

    Inventor： GREGORY G FREEMAN ,  GREENBERG DAVID R ,  JENG SHWU-JEN

    IPC: H01L21/331 ,  H01L29/10 ,  H01L29/737

    Abstract: PROBLEM TO BE SOLVED: To provide a method to form a high performance hetero-junction bipolar transistor. SOLUTION: The invention includes a process to form two pairs of spacers at both ends of an emitter pedestal. After a first pair of spacers 130 is formed, a first outer base region 100 is formed at both ends of an intrinsic base. A second pair of spacers 160 is formed above the first pair of spacers 130. Then, a second outer base region 140 is formed at both ends of the intrinsic base. Two pairs of spacers enable the first outer base and the second outer base to have different widths. This brings about a structure of complex outer base that is adjacent to an emitter 22 and not adjacent to a collector 20 and consequently a base parasitic resistance reduces with the reduction of parasitic capacitance between the collector and outer base.

    STEPPED COLLECTOR IMPLANTATION AND METHOD FOR MANUFACTURING THE SAME
    2.
    发明专利
    STEPPED COLLECTOR IMPLANTATION AND METHOD FOR MANUFACTURING THE SAME 审中-公开

    公开(公告)号：JP2002324806A

    公开(公告)日：2002-11-08

    申请号：JP2002075491

    申请日：2002-03-19

    Applicant: IBM

    Inventor： FREEMAN GREGORY G ,  JAGANNATHAN BASANTH ,  JENG SHWU-JEN ,  JOHNSON JEFFREY B

    IPC: H01L21/331 ,  H01L29/08 ,  H01L29/36 ,  H01L29/737

    Abstract: PROBLEM TO BE SOLVED: To provide an element structure and a method for manufacturing the same for suppressing an increase of an unnecessary capacitance in the element as small as possible and for improving a transistor characteristic. SOLUTION: In an integrated bi-polar circuit element, a stepped collector dopant profile reduces a transit time and a parasitic capacitance between an emitter and a collector due to a minimum increase of the parasitic capacitance. A shallow implantation reduces a width of a space charge region between a base and the collector, reduces a resistance, and individually optimizes a breakdown characteristic between the collector and the base. A deep implantation, then, links a buried collector to a sub-collector and provides a low resistance path to the sub-collector. The stepped collector dopant profile only gives the lowest effect against a capacitance the collector and the base outside an intrinsic region of the element. The reason is that the higher concentration dopant is compensated by an exogenous dopant outside the intrinsic region or is buried therein.

    A NON-SELF-ALIGNED SIGE HETEROJUNCTION BIPOLAR TRANSISTOR
    3.
    发明申请
    A NON-SELF-ALIGNED SIGE HETEROJUNCTION BIPOLAR TRANSISTOR 审中-公开
    非自对准信号异相双极晶体管

    公开(公告)号：WO03001584A8

    公开(公告)日：2004-05-27

    申请号：PCT/US0219789

    申请日：2002-06-19

    Applicant: IBM

    Inventor： JAGANNATHAN BASANTH ,  JENG SHWU-JEN ,  JOHNSON JEFFREY B ,  JOHNSON ROBB A ,  LANZEROTTI LOUIS D ,  STEIN KENNETH J ,  SUBBANNA SESHADRI

    IPC: H01L21/331 ,  H01L21/8249 ,  H01L29/737 ,  H01L31/11

    CPC classification number: H01L29/66242 ,  H01L21/8249 ,  H01L29/7378

    Abstract: A method for making a non-self-aligned, heterojunction bipolar transistor includes forming extrinsic base regions (70) with a PFET source/drain implant aligned with the polysilicon in an emitter stack but which are not directly aligned with an emitter opening defined in that stack. This is achieved by making the emitter pedestal (66) wider than the emitter opening. This advantageously removes the dependency of alignment between the extrinsic base regions and the emitter opening, thereby resulting in fewer process steps, reduced thermal cycles, and improved speed.

    Abstract translation: 一种用于制造非自对准的异质结双极晶体管的方法包括：在发射极堆叠中形成具有与多晶硅对准的PFET源极/漏极注入的非本征基极区域（70），但并不直接对准在该区域中限定的发射极开口 叠加。 这通过使发射器基座（66）比发射器开口更宽来实现。 这有利地消除了非本征基区和发射极开口之间的对准的依赖性，从而导致更少的工艺步骤，减少的热循环和改进的速度。

    Transistor structure having minimized parasitic effect and manufacturing method of same
    4.
    发明专利
    Transistor structure having minimized parasitic effect and manufacturing method of same 有权
    具有最小化的PARASITIC效应的晶体管结构及其制造方法

    公开(公告)号：JP2005244225A

    公开(公告)日：2005-09-08

    申请号：JP2005045016

    申请日：2005-02-22

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： GREENBERG DAVID R ,  JENG SHWU-JEN

    IPC: H01L21/331 ,  H01L29/08 ,  H01L29/423 ,  H01L29/72 ,  H01L29/73 ,  H01L29/732

    CPC classification number: H01L29/66287 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/42308 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

    Abstract: PROBLEM TO BE SOLVED: To provide a transistor having a minimized parasitic effect. SOLUTION: The transistor includes an emitter, having a recessed extrinsic emitter portion on an intrinsic emitter portion, and an intrinsic base portion electrically contacted with the intrinsic emitter portion and an extrinsic base portion electrically contacted with the intrinsic base portion, and also includes a base electrically isolated from a recessed extrinsic emitter portion by means of a pair of emitter/base spacers and a collector electrically contacted with the intrinsic base portion. The transistor can further include an intrinsic base, having a completely silicide upper surface, until it reaches the emitter/base spacers. The transistor can further include a base window opening in an active region. A method of forming the transistor is also included. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供具有最小化的寄生效应的晶体管。 解决方案：晶体管包括发射极，在本征发射极部分具有凹入的非本征发射极部分，以及与本征发射极部分电接触的本征基极部分和与本征基极部分电接触的非本征基极部分，以及 包括通过一对发射极/基极间隔物和与本征基极部电接触的集电体与凹入的外部发射极部分电隔离的基极。 晶体管可以进一步包括具有完全硅化物上表面的本征基极，直至其到达发射极/基极间隔物。 晶体管还可以包括在有源区域中的基部窗口开口。 还包括形成晶体管的方法。 版权所有（C）2005，JPO＆NCIPI

    7.
    发明专利
    未知

    公开(公告)号：DE69332013T2

    公开(公告)日：2003-01-30

    申请号：DE69332013

    申请日：1993-10-05

    Applicant: IBM

    Inventor： JENG SHWU-JEN ,  NATZLE WESLEY C ,  YU CHIENFAN

    IPC: H01L21/00 ,  H01L21/302 ,  H01L21/3065 ,  C23F4/00 ,  H01L21/311 ,  H01L21/306

    Abstract: New device and method are described for accurate etching and removal of thin layer by controlling the surface residence time, thickness and composition of reactant containing film. Etching of silicon dioxide at low pressure using a quartz crystal microbalance is illustrated. Usefulness of the invention in the manufacture of microelectronic devices is shown.

    8.
    发明专利
    未知

    公开(公告)号：AT219292T

    公开(公告)日：2002-06-15

    申请号：AT93480154

    申请日：1993-10-05

    Applicant: IBM

    Inventor： JENG SHWU-JEN ,  NATZLE WESLEY C ,  YU CHIENFAN

    IPC: C23F4/00 ,  H01L21/00 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/306

    Abstract: New device and method are described for accurate etching and removal of thin layer by controlling the surface residence time, thickness and composition of reactant containing film. Etching of silicon dioxide at low pressure using a quartz crystal microbalance is illustrated. Usefulness of the invention in the manufacture of microelectronic devices is shown.

    9.
    发明专利
    未知

    公开(公告)号：DE69332013D1

    公开(公告)日：2002-07-18

    申请号：DE69332013

    申请日：1993-10-05

    Applicant: IBM

    Inventor： JENG SHWU-JEN ,  NATZLE WESLEY C ,  YU CHIENFAN

    IPC: H01L21/00 ,  H01L21/302 ,  H01L21/3065 ,  C23F4/00 ,  H01L21/311 ,  H01L21/306

    Abstract: New device and method are described for accurate etching and removal of thin layer by controlling the surface residence time, thickness and composition of reactant containing film. Etching of silicon dioxide at low pressure using a quartz crystal microbalance is illustrated. Usefulness of the invention in the manufacture of microelectronic devices is shown.

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