公开(公告)号：EP1842240A4

公开(公告)日：2009-10-14

申请号：EP05826022

申请日：2005-12-02

Applicant: IBM

Inventor： CALLEGARI ALESSANDRO C ,  GRIBELYUK MICHAEL A ,  LACEY DIANNE L ,  MCFEELY FENTON R ,  SAENGER KATHERINE L ,  ZAFAR SUFI

IPC: H01L21/28 ,  C23C14/06 ,  C23C14/34 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/4966 ,  C23C14/0036 ,  C23C14/0635 ,  H01L21/28088 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665

公开(公告)号：JP2005123597A

公开(公告)日：2005-05-12

申请号：JP2004271982

申请日：2004-09-17

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： AJMERA ATUL C ,  BRYANT ANDRES ,  GILBERT PERCY V ,  GRIBELYUK MICHAEL A ,  MACIEJEWSKI EDWARD P ,  MO RENEE T ,  NARASIMHA SHREESH

IPC: H01L21/28 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/8238 ,  H01L23/52 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L21/02063 ,  H01L21/31116 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a gate electrode that avoids dielectric layer undercut during a silicide precleaning step. SOLUTION: A patterned gate stack includes a gate dielectric below a conductor having vertical sidewalls, and a dielectric layer is formed over the patterned gate stack and substrate surfaces. Nitride spacers are formed overlying the dielectric layer at each vertical sidewall. The dielectric layer on the substrate surface is removed using an etch process such that a portion of the dielectric layer underlying each spacer remains. Then, a nitride layer is deposited over the entire sample and subsequently removed by an etch process such that only a portion of the nitride film ("plug") remains. The plug seals and encapsulates the dielectric layer underlying the each spacer, thus preventing the dielectric material from being undercut during the subsequent silicide precleaning process. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种在硅化物预清洗步骤期间形成避免电介质层底切的栅电极的方法。 解决方案：图案化栅极堆叠包括在具有垂直侧壁的导体下方的栅极电介质，并且在图案化的栅极堆叠和衬底表面上形成介电层。 在每个垂直侧壁处形成覆盖电介质层的氮化物间隔物。 使用蚀刻工艺去除衬底表面上的电介质层，使得每个间隔物下面的电介质层的一部分保留。 然后，在整个样品上沉积氮化物层，然后通过蚀刻工艺去除，使得只有一部分氮化膜（“插塞”）保留。 塞子密封并封装每个间隔物下面的电介质层，从而防止在随后的硅化物预清洗过程中电介质材料被切下。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2005217400A

公开(公告)日：2005-08-11

申请号：JP2005011467

申请日：2005-01-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHAKRAVARTI ASHIMA B ,  DORIS BRUCE B ,  GHALI ROMANY ,  GLUSCHENKOV OLEG G ,  GRIBELYUK MICHAEL A ,  LEE WOO-HYEONG ,  MADAN ANITA

IPC: C23C16/24 ,  C23C16/46 ,  H01L21/00 ,  H01L21/205 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC classification number: C23C16/24 ,  C23C16/46 ,  H01L21/28035 ,  H01L21/32055 ,  H01L29/4925

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a polycrystalline silicon having hyperfine particle sizes.
SOLUTION: The method of forming a polycrystalline silicon having hyperfine particle sizes employs a differential heating of upper and lower surfaces of a substrate of a CVD apparatus, in which the lower surface of the substrate receives considerably more power than the upper surface, preferably more than 75% of the entire power; and in which the substrate is maintained during deposition at a temperature higher than 50°C above 550°C of crystallization temperature of silicon.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 待解决的问题：提供一种形成具有超细粒径的多晶硅的方法。 解决方案：形成具有超细粒度的多晶硅的方法采用CVD装置的基板的上表面和下表面的差加热，其中基板的下表面比上表面受到相当大的功率， 优选超过整个功率的75％; 并且其中在高于硅的结晶温度高于550℃的温度高于50℃的温度下沉积时，保持基板。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：WO2006076086A3

公开(公告)日：2009-04-16

申请号：PCT/US2005043552

申请日：2005-12-02

Applicant: IBM ,  CALLEGARI ALESSANDRO C ,  GRIBELYUK MICHAEL A ,  LACEY DIANNE L ,  MCFEELY FENTON R ,  SAENGER KATHERINE L ,  ZAFAR SUFI

Inventor： CALLEGARI ALESSANDRO C ,  GRIBELYUK MICHAEL A ,  LACEY DIANNE L ,  MCFEELY FENTON R ,  SAENGER KATHERINE L ,  ZAFAR SUFI

IPC: H01L29/94 ,  H01L29/76 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/4966 ,  C23C14/0036 ,  C23C14/0635 ,  H01L21/28088 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665

Abstract: A compound metal comprising TiC which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the TiC compound metal. Furthermore, the TiC metal compound of the present invention is a very efficient oxygen diffusion barrier at 1000°C allowing very aggressive equivalent oxide thickness (EOT) and inversion layer thickness scaling below 14 Å in a p-metal oxide semiconductor (pMOS) device.

Abstract translation: 提供了包含TiC的复合金属，其是在包括高k电介质和界面层的栅极堆叠上具有约4.75至约5.3，优选约5e的功函数的功函数的热电稳定的p型金属，以及 制造TiC复合金属的方法。 此外，本发明的TiC金属化合物在1000℃下是非常有效的氧扩散阻挡层，在p-金属氧化物半导体（pMOS）器件中允许非常有侵蚀性的等效氧化物厚度（EOT）和低于14的反型层厚度标度。

公开(公告)号：DE602005022493D1

公开(公告)日：2010-09-02

申请号：DE602005022493

申请日：2005-12-02

Applicant: IBM

Inventor： CALLEGARI ALESSANDRO C ,  GRIBELYUK MICHAEL A ,  LACEY DIANNE L ,  MCFEELY FENTON R ,  SAENGER KATHERINE L ,  ZAFAR SUFI

IPC: H01L29/94 ,  C23C14/06 ,  C23C14/34 ,  H01L29/49 ,  H01L29/51

公开(公告)号：AT475195T

公开(公告)日：2010-08-15

申请号：AT05826022

申请日：2005-12-02

Applicant: IBM

Inventor： CALLEGARI ALESSANDRO C ,  GRIBELYUK MICHAEL A ,  LACEY DIANNE L ,  MCFEELY FENTON R ,  SAENGER KATHERINE L ,  ZAFAR SUFI

IPC: H01L21/28 ,  C23C14/06 ,  C23C14/34 ,  H01L29/49 ,  H01L29/51

Abstract: A compound metal comprising TiC which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the TiC compound metal. Furthermore, the TiC metal compound of the present invention is a very efficient oxygen diffusion barrier at 1000° C. allowing very aggressive equivalent oxide thickness (EOT) and inversion layer thickness scaling below 14 Å in a p-metal oxide semiconductor (pMOS) device.