公开(公告)号：EP1846947A4

公开(公告)日：2009-04-15

申请号：EP05852630

申请日：2005-12-02

Applicant: IBM

Inventor： VEREECKEN PHILIPPE M ,  BASKER VEERARAGHAVAN ,  CABRAL CYRIL JR ,  COOPER EMANUEL I ,  DELIGIANNI HARIKLIA ,  FRANK MARTIN M ,  JAMMY RAJARAO ,  PARUCHURI VAMSI KRISHNA ,  SAENGER KATHERINE L ,  SHAO XIAOYAN

IPC: H01L21/302 ,  H01L29/745

CPC classification number: H01L21/2885 ,  C25D3/50 ,  C25D5/02 ,  C25D5/024 ,  C25D5/54 ,  C25D7/123 ,  C25D9/04 ,  C25F3/14 ,  H01L21/28079 ,  H01L21/28114 ,  H01L21/76885 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78648

Abstract: A method for electroplating a gate metal (9) or other conducting or semiconducting material on a gate dielectric (2) is provided. The method involves selecting a substrate (3, 4), dielectric layer, and electrolyte solution or melt, wherein the combination of the substrate, dielectric layer, and electrolyte solution or melt allow an electrochemical current to be generated at an interface between the dielectric layer and the electrolyte solution or melt.

公开(公告)号：EP1886342A4

公开(公告)日：2011-06-15

申请号：EP06770646

申请日：2006-05-18

Applicant: IBM

Inventor： FOGEL KEITH E ,  SAENGER KATHERINE L ,  SUNG CHUN-YUNG ,  YIN HAIZHOU

IPC: H01L21/336 ,  H01L21/76 ,  H01L21/8236

CPC classification number: H01L21/2022 ,  H01L21/76224 ,  H01L21/823807

Abstract: The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. In particular, this invention provides a melt-recrystallization ATR method, for use alone or in combination with non-melt-recrystallization ATR methods, in which selected Si regions bounded by dielectric-filled trenches are induced to undergo an orientation change by the steps of preamorphization, laser-induced melting, and corner-defect-free templated recrystallization from the melt.

公开(公告)号：WO2006130360A3

公开(公告)日：2007-06-14

申请号：PCT/US2006019417

申请日：2006-05-18

Applicant: IBM ,  FOGEL KEITH E ,  SAENGER KATHERINE L ,  SUNG CHUN-YUNG ,  YIN HAIZHOU

Inventor： FOGEL KEITH E ,  SAENGER KATHERINE L ,  SUNG CHUN-YUNG ,  YIN HAIZHOU

IPC: H01L21/336 ,  H01L21/76 ,  H01L21/8236

CPC classification number: H01L21/2022 ,  H01L21/76224 ,  H01L21/823807

Abstract: The present invention provides an improved amorphization/ templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. The process flow of the present invention solves two major difficulties not disclosed by prior art ATR methods: the creation of "corner defects" at the edges of amorphized Si regions bounded by trenches, and undesired orientation changes during a high temperature post-recrystallization defect-removal annealing of non-ATR'd regions not bounded by trenches. In particular, this invention provides a process flow comprisng the steps of (i) amorphization and low-temperature recrystallization performed in substrate regions free of trenches; (ii) formation of trench isolation regions that subsume the defective regions at the edge of the ATR'd regions, and (iii) a high-temperature defect-removal anneal performed with the trench isolation regions in place.

Abstract translation: 本发明提供了用于制造低缺陷密度混合取向基底的改进的非晶化/模板重结晶（ATR）方法。 用于混合取向衬底制造的ATR方法通常从具有第一取向键合到具有第二取向的第二Si层或衬底的Si层开始。 第一Si层的选定区域是非晶化的，然后通过使用第二Si层作为模板，再结晶成第二Si层的取向。 本发明的工艺流程解决了现有技术ATR方法未公开的两个主要困难：在由沟槽限定的非晶化Si区域的边缘处产生“角部缺陷”，以及在高温后再结晶缺陷 - 不由沟槽限定的非ATR区域的去除退火。 特别地，本发明提供一种工艺流程，包括以下步骤：（i）在没有沟槽的衬底区域中进行的非晶化和低温重结晶; （ii）形成沟槽隔离区域，其包围在ATR'd区域的边缘处的缺陷区域，以及（iii）在沟槽隔离区域中进行的高温缺陷去除退火。

公开(公告)号：WO2006116098A3

公开(公告)日：2008-10-30

申请号：PCT/US2006015107

申请日：2006-04-21

Applicant: IBM ,  DESOUZA JOEL P ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L ,  SUNG CHUN-YUNG ,  YANG MIN ,  YIN HAIZHOU

Inventor： DESOUZA JOEL P ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L ,  SUNG CHUN-YUNG ,  YANG MIN ,  YIN HAIZHOU

IPC: H01L29/04

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/7624 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/66636 ,  H01L29/7833

Abstract: In the claimed mixed-crystal-orientation channel FET, source/drain regions above the bonded interface 360 have the orientation of the upper semiconductor 350 and source/drain regions below the bonded interface 360 have the orientation of the lower semiconductor 370, so that each part of the source/drain has the same crystal orientation as the semiconductor material laterally adjacent to it. Optional source/drain extensions 392 are disposed entirely in the upper semiconductor layer 350. Optionally, the bonded interface 360 is situated towards the bottom of source/drain regions 380, leaving source/drains 380 mostly in upper semiconductor layer 350.

Abstract translation: 在所要求的混晶取向沟道FET中，键合界面360上方的源极/漏极区域具有上部半导体350的取向，并且键合界面360下方的源极/漏极区域具有下部半导体370的取向，使得每个 源极/漏极的一部分具有与横向相邻的半导体材料相同的晶体取向。 可选的源极/漏极延伸部分392完全设置在上部半导体层350中。可选地，接合界面360朝向源极/漏极区域380的底部设置，使得源极/漏极380大部分在上部半导体层350中。

公开(公告)号：WO2007130333A2

公开(公告)日：2007-11-15

申请号：PCT/US2007010411

申请日：2007-04-30

Applicant: IBM ,  BEDELL STEPHEN W ,  DESOUZA JOEL P ,  REN ZHIBIN ,  REZNICEK ALEXANDER ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L ,  SHAHIDI GHAVAM

Inventor： BEDELL STEPHEN W ,  DESOUZA JOEL P ,  REN ZHIBIN ,  REZNICEK ALEXANDER ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L ,  SHAHIDI GHAVAM

IPC: H01L21/8234

CPC classification number: H01L29/66628 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78684 ,  Y10S438/909 ,  Y10S438/943

Abstract: This invention teaches methods of combining ion implantation steps with in situ or ex situ heat treatments to avoid and/or minimize implant-induced amorphization (a potential problem for source/drain (SfD) regions in FETs in ultrathin silicon on insulator layers) and implant-induced plastic relaxation of strained S/D regions (a potential problem for strained channel FETs in which the channel strain is provided by embedded S/D regions lattice mismatched with an underlying substrate layer). In a first embodiment, ion implantation is combined with in situ heat treatment by performing the ion implantation at elevated temperature. In a second embodiment, ion implantation is combined withex situ heat treatments in a "divided-dose-anneal-in-between" (DDAB) scheme that avoids the need for tooling capable of performing hot implants.

Abstract translation: 本发明教导了将离子注入步骤与原位或非原位热处理组合以避免和/或最小化植入物诱导的非晶化（在绝缘体上的超薄硅层中的FET中的源/漏（SfD）区域的潜在问题）和植入物 诱导的应变S / D区域的塑性弛豫（对于通道应变由嵌入的S / D区域与下面的基底层不匹配而提供的应变通道FET的潜在问题）。 在第一实施例中，通过在升高的温度下进行离子注入将离子注入与原位热处理组合。 在第二实施例中，离子注入在“分剂量退火中间”（DDAB）方案中组合了原位热处理，避免了对能够进行热植入的加工的需要。

公开(公告)号：JP2006191029A

公开(公告)日：2006-07-20

申请号：JP2005363874

申请日：2005-12-16

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DE SOUZA JOEL P ,  OTT JOHN A ,  REZNICEK ALEXANDER ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L

IPC: H01L21/02

CPC classification number: H01L21/187 ,  H01L21/76251

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a bonding interface between Si having characteristics equal to that attained by hydrophobic bonding by removing an ultra thin interface oxide remaining after hydrophobic wafer bonding between Si.
SOLUTION: The interface oxide layer in the order of about 2-3 nm is dissolved and removed by, for example, high temperature annealing at 1,300-1,330°C only for 1-5 hours. The invention is most effectively used if the Si surface of a bonding interface has a different surface orientation as, for example, the Si surface with (100) orientation is bonded to the Si surface with (110) orientation. In more generous modes of this invention, an undesired material arranged on the bonding interface of two silicon-contained semiconductor materials can be removed by a similar annealing process. The surface crystal orientation, fine structure (single crystal, polycrystal, or amorphous), and elements of two silicon-contained semiconductor materials may or may not be identical.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供通过除去Si之间的疏水性晶片接合之后残留的超薄界面氧化物，形成具有与通过疏水接合获得的特性相同的特性的Si之间的结合界面的方法。 解决方案：通过例如1300-133℃的高温退火将约2-3nm量级的界面氧化物层溶解并除去1-5小时。 如果接合界面的Si表面具有不同的表面取向，则本发明是最有效的，因为例如具有（110）取向的具有（100）取向的Si表面结合到Si表面。 在本发明的更宽泛的模式中，可以通过类似的退火工艺去除布置在两个含硅半导体材料的结合界面上的不需要的材料。 表面晶体取向，精细结构（单晶，多晶或非晶）和两个含硅半导体材料的元素可以相同也可以不相同。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2006191028A

公开(公告)日：2006-07-20

申请号：JP2005363826

申请日：2005-12-16

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DE SOUZA JOEL P ,  FOGEL KEITH E ,  OTT JOHN ALBRECHT ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L

IPC: H01L21/20 ,  H01L21/324

CPC classification number: H01L21/26506 ,  H01L21/2022

Abstract: PROBLEM TO BE SOLVED: To provide a method for amorphization/template re-crystallization for changing orientation in the selected region of a silicon, without remaining defect of high density, by preparing an anneal process optimized to remove defects caused by damage due to injection, in a single crystal silicon. SOLUTION: The region of Si having a first crystal orientation is amorphised by iron-implantation, and is re-crystallized into the orientation of a template layer having different orientation, in an amorphising/template re-crystallization (ATR) process. A reoriented Si of low defective density in the process is formed by this method. More specifically, the invention relates to a high temperature annealing condition required for eliminating defects remaining in an Si-contained single crystal semiconductor material formed of the layer whose orientation is identical or different from the original orientation of amorphous layer by amorphising caused by ion-implantation and template re-crystallization. The main factor of that is a thermal process for removing defects remaining after initial re-crystallization annealing, in the temperature range of 1,250-1,330°C for several minutes to several hours. A reoriented Si of low defective density, formed by ATR, is provided as well for use with a hybrid orientation substrate. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供一种用于改变所选择的硅区域中的取向的无定形/模板再结晶的方法，而不存在高密度的缺陷，通过制备优化的消除由于损坏引起的缺陷的退火工艺 注入单晶硅。 解决方案：通过铁注入将具有第一晶体取向的Si区域非晶化，并且在非晶化/模板再结晶（ATR）工艺中，重新结晶成具有不同取向的模板层的取向。 通过该方法形成该方法中的低缺陷密度的重新取向的Si。 更具体地说，本发明涉及一种高温退火条件，用于消除由该离子注入引起的非晶形取向与非晶层的原始取向相同或不同的Si形成的含Si单晶半导体材料残留的缺陷 和模板再结晶。 其主要因素是在初始再结晶退火后，在1,250-133℃的温度范围内去除几分钟至数小时的缺陷的热处理。 还提供了由ATR形成的低缺陷密度的重新取向的Si，以及与混合取向基板一起使用。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2006041526A

公开(公告)日：2006-02-09

申请号：JP2005213971

申请日：2005-07-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KEVIN K CHAN ,  DE SOUZA JOEL P ,  REZNICEK ALEXANDER ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L

IPC: H01L21/76 ,  H01L21/02 ,  H01L21/265 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L21/84 ,  H01L21/76243 ,  H01L21/76267 ,  H01L27/1203 ,  H01L27/1207

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a device on a crystal of orientation which brings about optimal performance by providing separation by an oxygen implantation (SIMOX) method for the formation of a flat hybrid orientation semiconductor on insulator (SOI) substrate having a crystal of different orientation. SOLUTION: A method comprises steps of: selecting a substrate having a lower semiconductor layer having first crystal orientation separated from an upper semiconductor layer having second crystal orientation by a thin insulating layer; replacing the upper semiconductor layer of a selected region with epitaxial growth semiconductor having the first crystal orientation; (i) forming a padding insulating region in an epitaxial growth semiconductor material and (ii) thickening an insulating layer under the upper semiconductor layer using ion implantation and annealing methods; and forming a hybrid orientation substrate in which two semiconductor materials of different crystal orientation have substantially identical thickness and are arranged on the common padding insulating layer. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种通过提供通过氧注入（SIMOX）方法分离以形成绝缘体上的平坦混合取向半导体（SOI）的方向来制造取向晶体的装置的方法，该方法产生最佳性能 ）衬底具有不同取向的晶体。 解决方案：一种方法包括以下步骤：通过薄绝缘层，选择具有从具有第二晶体取向的上半导体层分离的具有第一晶体取向的下半导体层的衬底; 用具有第一晶体取向的外延生长半导体代替所选区域的上半导体层; （i）在外延生长半导体材料中形成填充绝缘区域，和（ii）使用离子注入和退火方法使上半导体层下方的绝缘层增厚; 以及形成混合取向基板，其中两个不同晶体取向的半导体材料具有基本上相同的厚度并且布置在公共衬垫绝缘层上。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2004214648A

公开(公告)日：2004-07-29

申请号：JP2003421653

申请日：2003-12-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： COLBURN MATTHEW E ,  HUANG ELBERT E ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH ,  SAENGER KATHERINE L

IPC: H01L23/12 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76808 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming in-layer and interlayer air bridge structures, in a large scale integrated circuit (VLSI) device, a very large scale integrated circuit (ULSI) device, and a high-performance package. SOLUTION: The method of forming low k (dielectric constant) and ultra-low k multilayer mutual connections on a substrate is provided with a process to form a pair of mutual connection, separated along a side face by an air gap and a support layer in a via level of a dual damascene structure which exists only under a metal wiring, a process to remove a sacrificial dielectric through a holed bridge layer to connect an upper surface of the mutual connection along the side face, a process of executing a multilayer level extraction of the sacrificial layer, a process of sealing the bridge by a controlled method, and a process of reducing the effective dielectric constant of a film holed by using a patterning technology of a quasi-optical lithography. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：EP1842240A4

公开(公告)日：2009-10-14

申请号：EP05826022

申请日：2005-12-02

Applicant: IBM

Inventor： CALLEGARI ALESSANDRO C ,  GRIBELYUK MICHAEL A ,  LACEY DIANNE L ,  MCFEELY FENTON R ,  SAENGER KATHERINE L ,  ZAFAR SUFI

IPC: H01L21/28 ,  C23C14/06 ,  C23C14/34 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/4966 ,  C23C14/0036 ,  C23C14/0635 ,  H01L21/28088 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665