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    A method of metallising an organic substrate so as to achieve improved adhesion of the metal.
    1.
    发明公开
    A method of metallising an organic substrate so as to achieve improved adhesion of the metal. 失效
    为了实现有机物体的金属化工艺在金属的粘附性。

    公开(公告)号：EP0206145A2

    公开(公告)日：1986-12-30

    申请号：EP86108025

    申请日：1986-06-12

    Applicant: IBM

    Inventor： CLABES JOACHIM GERHARD ,  HAHN PETER OTTO ,  HO PAUL SIU-CHUNG ,  LEFAKIS HARALAMBOS NMN ,  RUBLOFF GARY WAYNE

    IPC: B29C35/08 ,  B29C59/16 ,  C08J7/00 ,  C23C14/02 ,  C23C14/20 ,  C23C16/02

    CPC classification number: B29C59/16 ,  B29C2035/0872 ,  B29C2035/0877 ,  B29K2079/00 ,  C23C14/022 ,  C23C16/0263

    Abstract: Metal-organic substrate adhesion is improved by irradiating the substrate with low energy reactive ions, electrons, or photons to alter the chemical composition of a surface layer of the substrate to a depth of from about 1 nm to a few tens of nanometers. The energy of the incident reactive ions and electrons can be in the range of about 50 to 2000 eV, while the energy of the incident photons can be in the range of about 0.2 - 500 eV. Irradiation of the substrate can occur prior to or during metal deposition. For simultaneous metal deposition/particle irradiation, the arrival rates of the metal atoms and the substrate treatment particles are within a few orders of magnitude of one another. The low energy irradiation can be conducted at room temperature or elevated temperatures.

    Abstract translation: 金属 - 有机底物的粘附，通过照射与低能量的反应性的离子，电子或光子的衬底以从约1nm改变衬底的表面层的至的深度的化学成分到几十纳米米提高。 入射反应性离子和电子的能量可在约50至2000伏特的范围内，而入射光子的能量可在约0.2的范围内 - 500eV的。 基板的照射可以之前或期间金属沉积好发。 对于同时金属沉积/颗粒的照射下，金属原子的到达率与基板处理颗粒是彼此的大小的几个数量级之内。 低能量照射可以在室温下或升高的温度下进行。

    Noncontact testing of integrated circuits.
    2.
    发明公开
    Noncontact testing of integrated circuits. 失效
    非接触式测试集成电路。

    公开(公告)号：EP0205760A1

    公开(公告)日：1986-12-30

    申请号：EP86103212

    申请日：1986-03-11

    Applicant: IBM

    Inventor： BEHA JOHANNES GEORG ,  DREYFUS RUSSELL EARREN ,  RUBLOFF GARY WAYNE

    IPC: G01R31/26 ,  G01Q30/02 ,  G01Q30/16 ,  G01Q30/20 ,  G01R31/308 ,  H01L21/66 ,  G01R31/28

    CPC classification number: G01R31/308

    Abstract: Simultaneous noncontact testing of voltages across a full line of test sites (2) on an integrated circuit chip-to-test (1) is achieved with high time resolution using photoelectron emission induced by a pulsed laser (3) focussed to a line (4) on the chip-to-test, together with high speed electrostatic deflection perpendicular to the line focus. Photoelectrons produced by the line focus of pulsed laser light are imaged to a line on an array detector (5), the measured photoelectron intensities at array points along this line representing voltages at corresponding points along the line illuminated by the laser focus. High speed electrostatic deflection applied to plates (7) during the laser pulse, perpendicular to the direction of the line focus, disperses the line image - (column) on the array detector across a sequence of sites at right angles (rows), thereby revealing the time-dependence of voltages in the column of test sites with high time resolution (in the picosecond
    ' range).

    3.
    发明专利
    未知

    公开(公告)号：DE3675236D1

    公开(公告)日：1990-12-06

    申请号：DE3675236

    申请日：1986-03-04

    Applicant: IBM

    Inventor： BEHA JOHANNES GEORG ,  DREYFUS RUSSELL EARREN ,  HARTSTEIN ALLAN MARK ,  RUBLOFF GARY WAYNE

    IPC: G01R31/28 ,  G01R31/308 ,  H01L21/66 ,  H01L23/544

    Abstract: The method comprising covering metal test pads (4) of an integrated circuit chip-to-test (11), with a photon-transmissive passivation layer (2) susceptible to photon assisted tunneling, covering the layer (2) with a thin conductive photon-transparent overlayer (3), and then accessing the test pads through the passivation layer and conductive overlayer, by a pulsed laser to provide voltage-modulated photon-assisted tunneling through the insulation layer, to the conductive overlayer as an electron current, and detecting the resulting electron current, thus providing a nondestructive test of integrated circuits. The passivation, normally present to protect the integrated circuit, also lowers the threshold for photoelectron emission. The conductive overlayer acts as a photoelectron collector for the detector. A chip-to-test which is properly designed for photon assisted tunneling testing has test sites accessible to laser photons even though passivated. Such a chip-to-test may be nondestructively tested in air at one or several stages of its processing, without the sacrifices of mechanical probing or of bringing test sites out to output pads.

    4.
    发明专利
    未知

    公开(公告)号：DE69315370D1

    公开(公告)日：1998-01-08

    申请号：DE69315370

    申请日：1993-03-12

    Applicant: IBM

    Inventor： DANA STEPHANE SIMON ,  ANDERLE MARIANO ,  RUBLOFF GARY WAYNE ,  SCHROTT ALEJANDRO GABRIEL ,  LIEHR MICHAEL

    IPC: H01L21/205 ,  G11B5/73 ,  H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L33/00 ,  G11B5/64 ,  H01L21/3205

    Abstract: The fabrication of rough Si surfaces with control of the roughness density, roughness length scale, and morphology on a nanometer scale is disclosed using 1) a low pressure chemical vapor deposition (CVD) process, typically in the 1 - 5 mTorr range, and 2) initial surface conditions and operating parameters such that initial growth is nucleation-controlled, e.g., using a thermal SiO2 surface which is relatively unreactive to SiH4 at an operating temperature below about 700 DEG C, and typically in the range of 500 - 600 DEG C. This broad temperature window enhances the feasibility of manufacturing rough silicon surfaces with broad applications. Further, various methods are presented for achieving surface pretreatment to control the size and density of the initial nuclei preparatory to the performance of the foregoing fabrication process. In addition, a method is disclosed for producing on a substrate surface, directly and in-situ, a pattern of submicrometer sized dots such that the dot center surface density and the total dot surface area coverage can be precisely controlled, using the features of the fabrication process with additional steps to achieve the desired dots. Particular applications include fabricating rough Si surfaces as (1) electrodes for high capacitance density structures for high density DRAM and (2) as substrates for low-stiction magnetic disks.

    5.
    发明专利
    未知

    公开(公告)号：DE3667547D1

    公开(公告)日：1990-01-18

    申请号：DE3667547

    申请日：1986-03-11

    Applicant: IBM

    Inventor： BEHA JOHANNES GEORG ,  DREYFUS RUSSELL EARREN ,  RUBLOFF GARY WAYNE

    IPC: G01R31/26 ,  G01Q30/02 ,  G01Q30/16 ,  G01Q30/20 ,  G01R31/308 ,  H01L21/66 ,  G01R31/28

    Abstract: Simultaneous noncontact testing of voltages across a full line of test sites (2) on an integrated circuit chip-to-test (1) is achieved with high time resolution using photoelectron emission induced by a pulsed laser (3) focussed to a line (4) on the chip-to-test, together with high speed electrostatic deflection perpendicular to the line focus. Photoelectrons produced by the line focus of pulsed laser light are imaged to a line on an array detector (5), the measured photoelectron intensities at array points along this line representing voltages at corresponding points along the line illuminated by the laser focus. High speed electrostatic deflection applied to plates (7) during the laser pulse, perpendicular to the direction of the line focus, disperses the line image - (column) on the array detector across a sequence of sites at right angles (rows), thereby revealing the time-dependence of voltages in the column of test sites with high time resolution (in the picosecond ' range).

    8.
    发明专利
    未知

    公开(公告)号：DE69315370T2

    公开(公告)日：1998-05-28

    申请号：DE69315370

    申请日：1993-03-12

    Applicant: IBM

    Inventor： DANA STEPHANE SIMON ,  ANDERLE MARIANO ,  RUBLOFF GARY WAYNE ,  SCHROTT ALEJANDRO GABRIEL ,  LIEHR MICHAEL

    IPC: H01L21/205 ,  G11B5/73 ,  H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L33/00 ,  G11B5/64 ,  H01L21/3205

    Abstract: The fabrication of rough Si surfaces with control of the roughness density, roughness length scale, and morphology on a nanometer scale is disclosed using 1) a low pressure chemical vapor deposition (CVD) process, typically in the 1 - 5 mTorr range, and 2) initial surface conditions and operating parameters such that initial growth is nucleation-controlled, e.g., using a thermal SiO2 surface which is relatively unreactive to SiH4 at an operating temperature below about 700 DEG C, and typically in the range of 500 - 600 DEG C. This broad temperature window enhances the feasibility of manufacturing rough silicon surfaces with broad applications. Further, various methods are presented for achieving surface pretreatment to control the size and density of the initial nuclei preparatory to the performance of the foregoing fabrication process. In addition, a method is disclosed for producing on a substrate surface, directly and in-situ, a pattern of submicrometer sized dots such that the dot center surface density and the total dot surface area coverage can be precisely controlled, using the features of the fabrication process with additional steps to achieve the desired dots. Particular applications include fabricating rough Si surfaces as (1) electrodes for high capacitance density structures for high density DRAM and (2) as substrates for low-stiction magnetic disks.

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