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    DEVICE FOR EXECUTING SUB-ROUTINE CALLING AND RETURN OPERATION AND METHOD THEREFOR
    1.
    发明专利
    DEVICE FOR EXECUTING SUB-ROUTINE CALLING AND RETURN OPERATION AND METHOD THEREFOR 失效

    公开(公告)号：JPH11259298A

    公开(公告)日：1999-09-24

    申请号：JP925899

    申请日：1999-01-18

    Applicant: IBM

    Inventor： HILGENDORF ROLF ,  LAUB OLIVER ,  TAST HANS-WERNER

    IPC: G06F9/38 ,  G06F9/42 ,  G06F12/0875

    Abstract: PROBLEM TO BE SOLVED: To reduce a processing time for defining the target address of a sub-routine return instruction. SOLUTION: In a computer having a processor equipped with an instruction prefetch mechanism including a branch history table for storing the target address of plural branch instructions to be found in an instruction stream, a sub-routine calling and return operation is executed. In this case, the branch history table 22 includes a latent calling instruction tag and a return instruction tag. Each time the latent sub-routine calling instruction is found in the prefetch instruction stream, a pair of addresses including the calling target address of the instruction and the next successive instruction address are stored in a return identification stack 24. Then, a detected branch instruction activates associative retrieval for the next successive instructing part identifying the branch instruction as the return instruction by a matched entry in the return identification stack. Then, a pair of addresses included in the matched entry are transferred to a return cache 30 provided in parallel to the branch history table.

    3.
    发明专利
    未知

    公开(公告)号：DE19929051C2

    公开(公告)日：2001-10-04

    申请号：DE19929051

    申请日：1999-06-25

    Applicant: IBM

    Inventor： GAERTNER UTE ,  GETZLAFF KLAUS J ,  LAUB OLIVER ,  PFEFFER ERWIN

    IPC: G06F9/30 ,  G06F9/302 ,  G06F9/312 ,  G06F9/38 ,  G06F9/32 ,  G06F9/318

    Abstract: A method and system for renaming registers of said system is proposed in which mixed instruction sets, e.g. 32 bit and 64 bit instructions are carried out concurrently in one program. In case of an instruction sequence of a preceding 64 bit instruction and one or more 32 bit instructions to be executed in-order after the 64 bit instruction and where the 32 bit instructions having a data dependence to the preceding 64 bit instruction, said rest of the register range changed by the preceding 64 bit instruction is copied to the corresponding location in a target register of the succeeding 32 bit instruction, at least if the same logical register is specified by the 32 bit instruction as it was specified by the preceding 64 bit instruction. The copy source is addressed by the register number and hold in a list (28).

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