公开(公告)号：WO2007112432A3

公开(公告)日：2009-03-26

申请号：PCT/US2007065324

申请日：2007-03-28

Applicant: IBM ,  LIU YAOCHENG ,  GLUSCHENKOV OLEG ,  RIM KERN ,  MADAN ANITA ,  HOLT JUDSON

Inventor： LIU YAOCHENG ,  GLUSCHENKOV OLEG ,  RIM KERN ,  MADAN ANITA ,  HOLT JUDSON

IPC: H01L21/20 ,  H01L21/36

CPC classification number: H01L21/2022 ,  H01L21/2026 ,  H01L21/268 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/7848

Abstract: Expitaxial substitutional solid solutions of silicon carbon (101 ) can be obtained by an ultra-fast anneal of an amorphous carbon-containing silicon material. The anneal is performed at a temperature above the recrystallization point, but below the melting point of the material and preferably lasts for less than 100 milliseconds in this temperature regime. The anneal is preferably a flash anneal or laser anneal. This approach is able to produce epitaxial silicon and carbon-containing materials (101 ) with a substantial portion of the carbon atoms at substitutional lattice positions. The approach is especially useful in CMOS processes and other electronic device manufacture where the presence of epitaxial Si1-yCy, y

Abstract translation: 可以通过非晶态含碳硅材料的超快速退火获得硅碳（101）的外延替代固溶体。 退火在高于再结晶点的温度下进行，但低于材料的熔点，并且在该温度范围内优选持续小于100毫秒。 退火优选是闪光退火或激光退火。 该方法能够产生具有替代晶格位置的大部分碳原子的外延硅和含碳材料（101）。 该方法在CMOS工艺和其他电子器件制造中特别有用，其中外延Si1-yCy，y <0.1对于应变工程或带隙工程是需要的。

公开(公告)号：GB2492524A

公开(公告)日：2013-01-02

申请号：GB201220031

申请日：2011-04-08

Applicant: IBM

Inventor： CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON ,  LI JINGHONG ,  NEWBURY JOSEPH ,  ONTALUS VIOREL ,  PARK DAE-GYU ,  ZHU ZHENGMAO

IPC: H01L29/78 ,  H01L21/8238

Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include an FET gate stack 18 located on an upper surface of a semiconductor substrate 12. The FET gate stack includes source and drain extension regions 28 located within the semiconductor substrate at a footprint of the FET gate stack. A device channel 40 is also present between the source and drain extension regions and beneath the gate stack. The structure further includes embedded stressor elements 34 located on opposite sides of the FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes a lower layer of a first epitaxy 36 doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy 38 doped semiconductor material located atop the lower layer. The lower layer of the first epitaxy doped semiconductor material has a lower content of dopant as compared to the upper layer of the second epitaxy doped semiconductor material. The structure further includes a monolayer of dopant located within the upper layer of each of the embedded stressor elements. The monolayer of dopant is in direct contact with an edge of either the source extension region or the drain extension region.

公开(公告)号：SG137761A1

公开(公告)日：2007-12-28

申请号：SG2007033061

申请日：2007-05-10

Applicant: IBM ,  CHARTERED SEMICONDUCTOR MFG

Inventor： CHONG YUNG FU ,  LUO ZHIJIONG ,  HOLT JUDSON

Abstract: The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. A strained channel CMOS transistor structure (200) comprises a source stressor region (225) comprising a source extension stressor region (225A); and a drain stressor region (226) comprising a drain extension stressor region (226A); wherein a strained channel region (229) is formed between the source extension stessor region (225A) and the drain extension stressor region (226A), a width of said channel region (229) being defined by adjacent ends (225B, 226B) of said extension stressor regions (225A, 226A).

公开(公告)号：SG157397A1

公开(公告)日：2009-12-29

申请号：SG2009075987

申请日：2007-05-17

Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM

Inventor： ZHIJIONG LUO ,  HOLT JUDSON ,  FU CHONG YUNG

Abstract: The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. A strained channel CMOS transistor structure comprises a source stressor region comprising a source extension stressor region; and a drain stressor region comprising a drain extension stressor region; wherein a strained channel region is formed between the source extension stressor region and the drain extension stressor region, a width of said channel region being defined by adjacent ends of said extension stressor regions.

公开(公告)号：SG137798A1

公开(公告)日：2007-12-28

申请号：SG2007035751

申请日：2007-05-17

Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM

Inventor： ZHIJIONG LUO ,  HOLT JUDSON ,  FU CHONG YUNG

Abstract: The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. A strained channel CMOS transistor structure comprises a source stressor region comprising a source extension stressor region; and a drain stressor region comprising a drain extension stressor region; wherein a strained channel region is formed between the source extension stressor region and the drain extension stressor region, a width of said channel region being defined by adjacent ends of said extension stressor regions.