公开(公告)号：WO2011133339A3

公开(公告)日：2012-03-08

申请号：PCT/US2011031693

申请日：2011-04-08

Applicant: IBM ,  CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON R ,  LI JINGHONG ,  NEWBURY JOSEPH S ,  ONTALUS VIOREL ,  PARK DAE-GYU ,  ZHU ZHENGMAO

Inventor： CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON R ,  LI JINGHONG ,  NEWBURY JOSEPH S ,  ONTALUS VIOREL ,  PARK DAE-GYU ,  ZHU ZHENGMAO

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8228 ,  H01L27/092

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834

Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include an FET gate stack 18 located on an upper surface of a semiconductor substrate 12. The FET gate stack includes source and drain extension regions 28 located within the semiconductor substrate at a footprint of the FET gate stack. A device channel 40 is also present between the source and drain extension regions and beneath the gate stack. The structure further includes embedded stressor elements 34 located on opposite sides of the FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes a lower layer of a first epitaxy 36 doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy 38 doped semiconductor material located atop the lower layer. The lower layer of the first epitaxy doped semiconductor material has a lower content of dopant as compared to the upper layer of the second epitaxy doped semiconductor material. The structure further includes a monolayer of dopant located within the upper layer of each of the embedded stressor elements. The monolayer of dopant is in direct contact with an edge of either the source extension region or the drain extension region.

Abstract translation: 公开了在其中具有嵌入的应力元件的半导体结构。 所公开的结构包括位于半导体衬底12的上表面上的FET栅极堆叠18. FET栅极堆叠包括在FET栅极堆叠的覆盖区处位于半导体衬底内的源极和漏极延伸区域28。 器件沟道40也存在于源极延伸区域和漏极延伸区域之间以及栅极堆叠层下方。 该结构还包括位于FET栅极堆叠的相对侧并且位于半导体衬底内的嵌入式应力元件34。 每个嵌入的应力元件包括第一外延36掺杂半导体材料的下层，其具有不同于半导体衬底的晶格常数的晶格常数并且在器件沟道中施加应变，并且第二外延的上层 38掺杂的半导体材料位于下层的顶部。 与第二外延掺杂半导体材料的上层相比，第一外延掺杂半导体材料的下层具有较低的掺杂剂含量。 该结构还包括位于每个嵌入的应力元件的上层内的掺杂剂单层。 掺杂剂的单层与源极延伸区域或漏极延伸区域的边缘直接接触。

公开(公告)号：WO2011162977A3

公开(公告)日：2012-03-15

申请号：PCT/US2011039892

申请日：2011-06-10

Applicant: IBM ,  CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON R ,  JOHNSON JEFFREY B ,  LI JINGHONG ,  PARK DAE-GYU ,  ZHU ZHENGMAO

Inventor： CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON R ,  JOHNSON JEFFREY B ,  LI JINGHONG ,  PARK DAE-GYU ,  ZHU ZHENGMAO

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7834 ,  H01L29/7848

Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack (18) located on an upper surface of a semiconductor substrate (12). The at least one FET gate stack includes source and drain extension regions (28) located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel (40) is also present between the source and drain extension regions (28) and beneath the at least one gate stack (18). The structure further includes embedded stressor elements (33) located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes, from bottom to top, a first layer of a first epitaxy doped semiconductor material (35) having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, a second layer of a second epitaxy doped semiconductor material (36) located atop the first layer, and a delta monolayer of dopant located on an upper surface of the second layer. The structure further includes a metal semiconductor alloy contact (45) located directly on an upper surface of the delta monolayer (37).

Abstract translation: 公开了在其中具有嵌入的应力元件的半导体结构。 所公开的结构包括位于半导体衬底（12）的上表面上的至少一个FET栅叠层（18）。 所述至少一个FET栅极堆叠包括位于所述至少一个FET栅极堆叠中的覆盖区内的所述半导体衬底内的源极和漏极延伸区域（28）。 器件通道（40）也存在于源极和漏极延伸区域（28）之间并且在至少一个栅极堆叠（18）下方。 该结构还包括位于至少一个FET栅极堆叠的相对侧上并且在半导体衬底内的嵌入式应力元件（33）。 每个嵌入式应力元件包括从底部到顶部具有不同于半导体衬底的晶格常数的晶格常数的第一外延掺杂半导体材料（35）的第一层，并且在器件沟道中施加应变， 位于第一层顶部的第二外延掺杂半导体材料（36）的第二层和位于第二层的上表面上的掺杂剂的Δ单层。 该结构还包括直接位于三角单层（37）的上表面上的金属半导体合金接触（45）。

公开(公告)号：GB2492524A

公开(公告)日：2013-01-02

申请号：GB201220031

申请日：2011-04-08

Applicant: IBM

Inventor： CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON ,  LI JINGHONG ,  NEWBURY JOSEPH ,  ONTALUS VIOREL ,  PARK DAE-GYU ,  ZHU ZHENGMAO

IPC: H01L29/78 ,  H01L21/8238

Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include an FET gate stack 18 located on an upper surface of a semiconductor substrate 12. The FET gate stack includes source and drain extension regions 28 located within the semiconductor substrate at a footprint of the FET gate stack. A device channel 40 is also present between the source and drain extension regions and beneath the gate stack. The structure further includes embedded stressor elements 34 located on opposite sides of the FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes a lower layer of a first epitaxy 36 doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy 38 doped semiconductor material located atop the lower layer. The lower layer of the first epitaxy doped semiconductor material has a lower content of dopant as compared to the upper layer of the second epitaxy doped semiconductor material. The structure further includes a monolayer of dopant located within the upper layer of each of the embedded stressor elements. The monolayer of dopant is in direct contact with an edge of either the source extension region or the drain extension region.

公开(公告)号：GB2494608B

公开(公告)日：2013-09-04

申请号：GB201300789

申请日：2011-06-10

Applicant: IBM

Inventor： CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON R ,  JOHNSON JEFFREY B ,  LI JINGHONG ,  PARK DAE-GYU ,  ZHU ZHENGMAO

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66

Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack located on an upper surface of a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. The structure further includes embedded stressor elements located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes, from bottom to top, a first layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, a second layer of a second epitaxy doped semiconductor material located atop the first layer, and a delta monolayer of dopant located on an upper surface of the second layer. The structure further includes a metal semiconductor alloy contact located directly on an upper surface of the delta monolayer.

公开(公告)号：DE112011101378T8

公开(公告)日：2013-05-08

申请号：DE112011101378

申请日：2011-06-10

Applicant: IBM

Inventor： CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON R ,  JOHNSON JEFFREY B ,  LI JINGHONG ,  ZHU ZHENGMAO ,  PARK DAE-GUY

IPC: H01L29/78 ,  H01L21/336

公开(公告)号：DE112011101433T5

公开(公告)日：2013-03-28

申请号：DE112011101433

申请日：2011-04-08

Applicant: IBM

Inventor： CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON R ,  LI JINGHONG ,  NEWBURY JOSEPH S ,  ONTALUS VIOREL ,  PARK DAE-GYU ,  ZHU ZHENGMAO

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8228 ,  H01L27/092

Abstract: Es werden Halbleiterstrukturen mit eingebetteten Stressorelementen offenbart. Die offenbarten Strukturen umfassen einen FET-Gate-Stapel 18, der sich auf einer oberen Oberfläche eines Halbleitersubstrats 12 befindet. Der FET-Gate-Stapel umfasst den Source- und den Drain-Erweiterungsbereich 28, die sich in dem Halbleitersubstrat an einer Auflagefläche des FET-Gate-Stapels befinden. Zwischen dem Source- und dem Drain-Erweiterungsbereich und unterhalb des Gate-Stapels ist außerdem ein Bauelementkanal 40 vorhanden. Die Struktur umfasst weiter eingebettete Stressorelemente 34, die sich auf entgegengesetzten Seiten des FET-Gate-Stapels und in dem Halbleitersubstrat befinden. Jedes der eingebetteten Stressorelemente enthält eine untere Schicht eines ersten dotierten Epitaxie-Halbleitermaterials 36 mit einer Gitterkonstante, die sich von einer Gitterkonstante des Halbleitersubstrats unterscheidet und eine Verspannung in den Bauelementkanal überträgt, und eine obere Schicht eines zweiten dotierten Epitaxie-Halbleitermaterials 38, die sich auf der unteren Schicht befindet. Die untere Schicht des ersten dotierten Epitaxie-Halbleitermaterials weist im Vergleich mit der oberen Schicht des zweiten dotierten Epitaxie-Halbleitermaterials einen geringeren Dotierstoffgehalt auf. Die Struktur umfasst weiter eine Dotierstoff-Monoschicht, die sich in der oberen Schicht jedes der eingebetteten Stressorelemente befindet. Die Dotierstoff-Monoschicht steht mit einem Rand entweder des Source-Erweiterungsbereichs oder des Drain-Erweiterungsbereichs in direktem Kontakt.

公开(公告)号：GB2494608A

公开(公告)日：2013-03-13

申请号：GB201300789

申请日：2011-06-10

Applicant: IBM

Inventor： CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON R ,  JOHNSON JEFFREY B ,  LI JINGHONG ,  PARK DAE-GYU ,  ZHU ZHENGMAO

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66

Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack (18) located on an upper surface of a semiconductor substrate (12). The at least one FET gate stack includes source and drain extension regions (28) located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel (40) is also present between the source and drain extension regions (28) and beneath the at least one gate stack (18). The structure further includes embedded stressor elements (33) located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes, from bottom to top, a first layer of a first epitaxy doped semiconductor material (35) having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, a second layer of a second epitaxy doped semiconductor material (36) located atop the first layer, and a delta monolayer of dopant located on an upper surface of the second layer. The structure further includes a metal semiconductor alloy contact (45) located directly on an upper surface of the delta monolayer (37).

公开(公告)号：DE112011101378T5

公开(公告)日：2013-03-07

申请号：DE112011101378

申请日：2011-06-10

Applicant: IBM

Inventor： CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON R ,  JOHNSON JEFFREY B ,  LI JINGHONG ,  PARK DAE-GYU ,  ZHU ZHENGMAO

IPC: H01L29/78 ,  H01L21/336

Abstract: Es werden Halbleiterstrukturen offenbart, welche darin eingebettete Stressorelemente aufweisen. Die offenbarten Strukturen weisen mindestens einen FET-Gate-Stapel (18) auf, welcher auf einer oberen Fläche eines Halbleitersubstrats (12) angeordnet ist. Der mindestens eine FET-Gate-Stapel weist Source- und Drain-Ausdehnungszonen (28) auf, welche innerhalb des Halbleitersubstrats an einer Standfläche des mindestens einen FET-Gate-Stapels angeordnet sind. Ein Einheitskanal (40) ist zwischen der Source- und Drain-Ausdehnungszone (28) und unterhalb des mindestens einen Gate-Stapels (18) ebenfalls vorhanden. Die Struktur weist ferner eingebettete Stressorelemente (33) auf, welche auf gegenüberliegenden Seiten des mindestens einen FET-Gate-Stapels und innerhalb des Halbleitersubstrats angeordnet sind. Jedes eingebettete Stressorelement weist von unten nach oben eine erste Schicht eines ersten Epitaxie-dotierten Halbleitermaterials (35), welches eine Gitterkonstante aufweist, die sich von einer Gitterkonstante des Halbleitermaterials unterscheidet und zu einer Spannung in dem Einheitskanal führt, eine zweite Schicht eines zweiten Epitaxie-dotierten Halbleitermaterials (36), die auf der ersten Schicht angeordnet ist, und eine Delta-Monoschicht eines Dotierstoffs auf, die auf einer oberen Fläche der zweiten Schicht angeordnet ist. Die Struktur weist ferner einen Metall-Halbleiter-Legierungs-Kontakt (45) auf, welcher direkt auf einer oberen Fläche der Delta-Monoschicht (37) angeordnet ist.

公开(公告)号：GB2492524B

公开(公告)日：2013-05-22

申请号：GB201220031

申请日：2011-04-08

Applicant: IBM

Inventor： CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON R ,  LI JINGHONG ,  NEWBURY JOSEPH ,  ONTALUS VIOREL C ,  PARK DAE-GYU ,  ZHU ZHENGMAO

IPC: H01L29/78 ,  H01L21/8238

公开(公告)号：SG184824A1

公开(公告)日：2012-11-29

申请号：SG2012075586

申请日：2011-06-10

Applicant: IBM

Inventor： CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON R ,  JOHNSON JEFFREY B ,  LI JINGHONG ,  PARK DAE-GYU ,  ZHU ZHENGMAO

Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack (18) located on an upper surface of a semiconductor substrate (12). The at least one FET gate stack includes source and drain extension regions (28) located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel (40) is also present between the source and drain extension regions (28) and beneath the at least one gate stack (18). The structure further includes embedded stressor elements (33) located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes, from bottom to top, a first layer of a first epitaxy doped semiconductor material (35) having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, a second layer of a second epitaxy doped semiconductor material (36) located atop the first layer, and a delta monolayer of dopant located on an upper surface of the second layer. The structure further includes a metal semiconductor alloy contact (45) located directly on an upper surface of the delta monolayer (37).