公开(公告)号：JP2011054972A

公开(公告)日：2011-03-17

申请号：JP2010195552

申请日：2010-09-01

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： JOHNSON JEFFREY BOWMAN ,  ONTALUS VIOREL

IPC: H01L29/78

CPC classification number: H01L29/66636 ,  H01L21/26586 ,  H01L29/6653 ,  H01L29/66659 ,  H01L29/7848

Abstract: PROBLEM TO BE SOLVED: To provide a structure having asymmetric source and drain regions.
SOLUTION: A method forms the structure that has a substrate having at least one semiconductor channel region, a gate dielectric layer on the upper surface of the substrate over the semiconductor channel region, and a gate conductor on the gate dielectric layer. Asymmetric sidewall spacers are located on the sidewalls of the gate conductor and asymmetric source and drain regions are located, within the substrate, adjacent to the semiconductor channel region. One source/drain region is positioned closer to the midpoint of the gate conductor than is the other source/drain region. The source and drain regions comprise a material that induces physical stress upon the semiconductor channel region.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供具有不对称源极和漏极区域的结构。 解决方案：一种方法形成具有衬底的结构，该衬底具有至少一个半导体沟道区，在半导体沟道区上的衬底上表面上的栅介质层和栅介质层上的栅极导体。 不对称侧壁间隔物位于栅极导体的侧壁上，不对称的源极和漏极区位于衬底内，邻近半导体沟道区。 一个源极/漏极区域比另一个源极/漏极区域更靠近栅极导体的中点定位。 源极和漏极区域包括在半导体沟道区域上引起物理应力的材料。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：WO2011133339A3

公开(公告)日：2012-03-08

申请号：PCT/US2011031693

申请日：2011-04-08

Applicant: IBM ,  CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON R ,  LI JINGHONG ,  NEWBURY JOSEPH S ,  ONTALUS VIOREL ,  PARK DAE-GYU ,  ZHU ZHENGMAO

Inventor： CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON R ,  LI JINGHONG ,  NEWBURY JOSEPH S ,  ONTALUS VIOREL ,  PARK DAE-GYU ,  ZHU ZHENGMAO

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8228 ,  H01L27/092

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834

Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include an FET gate stack 18 located on an upper surface of a semiconductor substrate 12. The FET gate stack includes source and drain extension regions 28 located within the semiconductor substrate at a footprint of the FET gate stack. A device channel 40 is also present between the source and drain extension regions and beneath the gate stack. The structure further includes embedded stressor elements 34 located on opposite sides of the FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes a lower layer of a first epitaxy 36 doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy 38 doped semiconductor material located atop the lower layer. The lower layer of the first epitaxy doped semiconductor material has a lower content of dopant as compared to the upper layer of the second epitaxy doped semiconductor material. The structure further includes a monolayer of dopant located within the upper layer of each of the embedded stressor elements. The monolayer of dopant is in direct contact with an edge of either the source extension region or the drain extension region.

Abstract translation: 公开了在其中具有嵌入的应力元件的半导体结构。 所公开的结构包括位于半导体衬底12的上表面上的FET栅极堆叠18. FET栅极堆叠包括在FET栅极堆叠的覆盖区处位于半导体衬底内的源极和漏极延伸区域28。 器件沟道40也存在于源极延伸区域和漏极延伸区域之间以及栅极堆叠层下方。 该结构还包括位于FET栅极堆叠的相对侧并且位于半导体衬底内的嵌入式应力元件34。 每个嵌入的应力元件包括第一外延36掺杂半导体材料的下层，其具有不同于半导体衬底的晶格常数的晶格常数并且在器件沟道中施加应变，并且第二外延的上层 38掺杂的半导体材料位于下层的顶部。 与第二外延掺杂半导体材料的上层相比，第一外延掺杂半导体材料的下层具有较低的掺杂剂含量。 该结构还包括位于每个嵌入的应力元件的上层内的掺杂剂单层。 掺杂剂的单层与源极延伸区域或漏极延伸区域的边缘直接接触。

公开(公告)号：DE112011101433T5

公开(公告)日：2013-03-28

申请号：DE112011101433

申请日：2011-04-08

Applicant: IBM

Inventor： CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON R ,  LI JINGHONG ,  NEWBURY JOSEPH S ,  ONTALUS VIOREL ,  PARK DAE-GYU ,  ZHU ZHENGMAO

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8228 ,  H01L27/092

Abstract: Es werden Halbleiterstrukturen mit eingebetteten Stressorelementen offenbart. Die offenbarten Strukturen umfassen einen FET-Gate-Stapel 18, der sich auf einer oberen Oberfläche eines Halbleitersubstrats 12 befindet. Der FET-Gate-Stapel umfasst den Source- und den Drain-Erweiterungsbereich 28, die sich in dem Halbleitersubstrat an einer Auflagefläche des FET-Gate-Stapels befinden. Zwischen dem Source- und dem Drain-Erweiterungsbereich und unterhalb des Gate-Stapels ist außerdem ein Bauelementkanal 40 vorhanden. Die Struktur umfasst weiter eingebettete Stressorelemente 34, die sich auf entgegengesetzten Seiten des FET-Gate-Stapels und in dem Halbleitersubstrat befinden. Jedes der eingebetteten Stressorelemente enthält eine untere Schicht eines ersten dotierten Epitaxie-Halbleitermaterials 36 mit einer Gitterkonstante, die sich von einer Gitterkonstante des Halbleitersubstrats unterscheidet und eine Verspannung in den Bauelementkanal überträgt, und eine obere Schicht eines zweiten dotierten Epitaxie-Halbleitermaterials 38, die sich auf der unteren Schicht befindet. Die untere Schicht des ersten dotierten Epitaxie-Halbleitermaterials weist im Vergleich mit der oberen Schicht des zweiten dotierten Epitaxie-Halbleitermaterials einen geringeren Dotierstoffgehalt auf. Die Struktur umfasst weiter eine Dotierstoff-Monoschicht, die sich in der oberen Schicht jedes der eingebetteten Stressorelemente befindet. Die Dotierstoff-Monoschicht steht mit einem Rand entweder des Source-Erweiterungsbereichs oder des Drain-Erweiterungsbereichs in direktem Kontakt.

公开(公告)号：DE102012217489A1

公开(公告)日：2013-04-18

申请号：DE102012217489

申请日：2012-09-26

Applicant: IBM

Inventor： WEHELLA-GAMAGE DEEPAL ,  ONTALUS VIOREL

IPC: H01L21/336 ,  H01L21/283 ,  H01L21/76 ,  H01L21/84 ,  H01L29/78

Abstract: Eine Ausführungsform der vorliegenden Erfindung stellt ein Verfahren zum Bilden von Transistoren, z. B. Transistoren mit schmalem Kanal, bereit. Das Verfahren beinhaltet das Erzeugen einer Transistorzone in einem Substrat, wobei die Transistorzone durch eine oder mehrere Zonen flacher Grabenisolierungen (STI), die in dem Substrat gebildet sind, von dem Rest des Substrats getrennt wird, so dass sie eine Kanalzone, eine Source-Zone und eine Drain-Zone aufweist; wobei die STI-Zonen eine Höhe aufweisen, die höher als die Transistorzone des Substrats ist; und wobei die Kanalzone einen auf ihr befindlichen Gate-Stapel aufweist; das Bilden von Abstandhaltern an Seitenwänden der STI-Zonen über der Transistorzone; das Erzeugen von Aussparungen in der Source-Zone und der Drain-Zone, wobei die Abstandhalter zumindest einen Abschnitt des Materials des Substrats unterhalb der Abstandhalter entlang Seitenwänden der STI-Zonen schützen; und das epitaxiale Anwachsen von Source- und Drain-Zone des Transistors in den Aussparungen.

公开(公告)号：GB2495575A

公开(公告)日：2013-04-17

申请号：GB201213195

申请日：2012-07-25

Applicant: IBM

Inventor： WEHELLA-GAMAGE DEEPAL ,  ONTALUS VIOREL

IPC: H01L29/78 ,  H01L21/762

Abstract: A method of forming transistors 210, 220, such as narrow channel transistors, in which transistor regions 102a, 102b are created in a substrate, the transistor regions each being separated from the rest of the substrate by one or more shallow trench isolation (STI) regions 105 formed in the substrate; the STI regions having a height higher than the transistor regions of the substrate and channel regions of the transistors having gate stacks on top thereof; spacers 202 are formed at sidewalls of the STI regions above the transistor regions; recesses are created to form source and drain regions of the transistors with the spacers overhanging the substrate to preserve at least a portion of substrate material underneath the spacers along sidewalls of the STI regions; and source and drain stressor regions 204, 205 are epitaxially grown in the recesses.

公开(公告)号：GB2495575B

公开(公告)日：2015-12-16

申请号：GB201213195

申请日：2012-07-25

Applicant: IBM

Inventor： WEHELLA-GAMAGE DEEPAL ,  ONTALUS VIOREL

IPC: H01L29/78 ,  H01L21/762

Abstract: Embodiment of the present invention provides a method of forming transistors such as narrow channel transistors. The method includes creating a transistor region in a substrate; the transistor region being separated from rest of the substrate, by one or more shallow trench isolation (STI) regions formed in the substrate, to include a channel region, a source region, and a drain region; the STI regions having a height higher than the transistor region of the substrate; and the channel region having a gate stack on top thereof; forming spacers at sidewalls of the STI regions above the transistor region; creating recesses in the source region and the drain region with the spacers preserving at least a portion of material of the substrate underneath the spacers along sidewalls of the STI regions; and epitaxially growing source and drain of the transistor in the recesses.

公开(公告)号：GB2492524A

公开(公告)日：2013-01-02

申请号：GB201220031

申请日：2011-04-08

Applicant: IBM

Inventor： CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON ,  LI JINGHONG ,  NEWBURY JOSEPH ,  ONTALUS VIOREL ,  PARK DAE-GYU ,  ZHU ZHENGMAO

IPC: H01L29/78 ,  H01L21/8238

Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include an FET gate stack 18 located on an upper surface of a semiconductor substrate 12. The FET gate stack includes source and drain extension regions 28 located within the semiconductor substrate at a footprint of the FET gate stack. A device channel 40 is also present between the source and drain extension regions and beneath the gate stack. The structure further includes embedded stressor elements 34 located on opposite sides of the FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes a lower layer of a first epitaxy 36 doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy 38 doped semiconductor material located atop the lower layer. The lower layer of the first epitaxy doped semiconductor material has a lower content of dopant as compared to the upper layer of the second epitaxy doped semiconductor material. The structure further includes a monolayer of dopant located within the upper layer of each of the embedded stressor elements. The monolayer of dopant is in direct contact with an edge of either the source extension region or the drain extension region.