公开(公告)号：EP1872409A4

公开(公告)日：2009-12-30

申请号：EP06750619

申请日：2006-04-19

Applicant: IBM

Inventor： ZHU WENJUAN ,  CHUDZIK MICHAEL P ,  GLUSCHENKOV OLEG ,  PARK DAE-GYU ,  SEKIGUCHI AKIHISA

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/336 ,  H01L29/51

CPC classification number: H01L21/28185 ,  H01L21/28097 ,  H01L21/28229 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517

公开(公告)号：WO2011133339A3

公开(公告)日：2012-03-08

申请号：PCT/US2011031693

申请日：2011-04-08

Applicant: IBM ,  CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON R ,  LI JINGHONG ,  NEWBURY JOSEPH S ,  ONTALUS VIOREL ,  PARK DAE-GYU ,  ZHU ZHENGMAO

Inventor： CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON R ,  LI JINGHONG ,  NEWBURY JOSEPH S ,  ONTALUS VIOREL ,  PARK DAE-GYU ,  ZHU ZHENGMAO

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8228 ,  H01L27/092

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834

Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include an FET gate stack 18 located on an upper surface of a semiconductor substrate 12. The FET gate stack includes source and drain extension regions 28 located within the semiconductor substrate at a footprint of the FET gate stack. A device channel 40 is also present between the source and drain extension regions and beneath the gate stack. The structure further includes embedded stressor elements 34 located on opposite sides of the FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes a lower layer of a first epitaxy 36 doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy 38 doped semiconductor material located atop the lower layer. The lower layer of the first epitaxy doped semiconductor material has a lower content of dopant as compared to the upper layer of the second epitaxy doped semiconductor material. The structure further includes a monolayer of dopant located within the upper layer of each of the embedded stressor elements. The monolayer of dopant is in direct contact with an edge of either the source extension region or the drain extension region.

Abstract translation: 公开了在其中具有嵌入的应力元件的半导体结构。 所公开的结构包括位于半导体衬底12的上表面上的FET栅极堆叠18. FET栅极堆叠包括在FET栅极堆叠的覆盖区处位于半导体衬底内的源极和漏极延伸区域28。 器件沟道40也存在于源极延伸区域和漏极延伸区域之间以及栅极堆叠层下方。 该结构还包括位于FET栅极堆叠的相对侧并且位于半导体衬底内的嵌入式应力元件34。 每个嵌入的应力元件包括第一外延36掺杂半导体材料的下层，其具有不同于半导体衬底的晶格常数的晶格常数并且在器件沟道中施加应变，并且第二外延的上层 38掺杂的半导体材料位于下层的顶部。 与第二外延掺杂半导体材料的上层相比，第一外延掺杂半导体材料的下层具有较低的掺杂剂含量。 该结构还包括位于每个嵌入的应力元件的上层内的掺杂剂单层。 掺杂剂的单层与源极延伸区域或漏极延伸区域的边缘直接接触。

公开(公告)号：WO2011162977A3

公开(公告)日：2012-03-15

申请号：PCT/US2011039892

申请日：2011-06-10

Applicant: IBM ,  CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON R ,  JOHNSON JEFFREY B ,  LI JINGHONG ,  PARK DAE-GYU ,  ZHU ZHENGMAO

Inventor： CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON R ,  JOHNSON JEFFREY B ,  LI JINGHONG ,  PARK DAE-GYU ,  ZHU ZHENGMAO

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7834 ,  H01L29/7848

Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack (18) located on an upper surface of a semiconductor substrate (12). The at least one FET gate stack includes source and drain extension regions (28) located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel (40) is also present between the source and drain extension regions (28) and beneath the at least one gate stack (18). The structure further includes embedded stressor elements (33) located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes, from bottom to top, a first layer of a first epitaxy doped semiconductor material (35) having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, a second layer of a second epitaxy doped semiconductor material (36) located atop the first layer, and a delta monolayer of dopant located on an upper surface of the second layer. The structure further includes a metal semiconductor alloy contact (45) located directly on an upper surface of the delta monolayer (37).

Abstract translation: 公开了在其中具有嵌入的应力元件的半导体结构。 所公开的结构包括位于半导体衬底（12）的上表面上的至少一个FET栅叠层（18）。 所述至少一个FET栅极堆叠包括位于所述至少一个FET栅极堆叠中的覆盖区内的所述半导体衬底内的源极和漏极延伸区域（28）。 器件通道（40）也存在于源极和漏极延伸区域（28）之间并且在至少一个栅极堆叠（18）下方。 该结构还包括位于至少一个FET栅极堆叠的相对侧上并且在半导体衬底内的嵌入式应力元件（33）。 每个嵌入式应力元件包括从底部到顶部具有不同于半导体衬底的晶格常数的晶格常数的第一外延掺杂半导体材料（35）的第一层，并且在器件沟道中施加应变， 位于第一层顶部的第二外延掺杂半导体材料（36）的第二层和位于第二层的上表面上的掺杂剂的Δ单层。 该结构还包括直接位于三角单层（37）的上表面上的金属半导体合金接触（45）。

公开(公告)号：WO2008106244A3

公开(公告)日：2010-03-18

申请号：PCT/US2008051067

申请日：2008-01-15

Applicant: IBM ,  CHUDZIK MICHAEL P ,  HE WEI ,  MO RENEE T ,  MOUMEN NAIM ,  NARAYANAN VIJAY ,  PARK DAE-GYU ,  PARUCHURI VAMSI K

Inventor： CHUDZIK MICHAEL P ,  HE WEI ,  MO RENEE T ,  MOUMEN NAIM ,  NARAYANAN VIJAY ,  PARK DAE-GYU ,  PARUCHURI VAMSI K

IPC: H01L21/335

CPC classification number: H01L21/823807 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/78 ,  H01L29/7845

Abstract: A gate structure (200) for complementary metal oxide semiconductor (CMOS) devices includes a first gate stack (116) having a first gate dielectric layer (102) formed over a substrate (100), and a first metal layer (106) formed over the first gate dielectric layer. A second gate stack (118) includes a second gate dielectric layer (102) formed over the substrate and a second metal layer (110) formed over the second gate dielectric layer. The first metal layer is formed in manner so as to impart a tensile stress on the substrate, and the second metal layer is formed in a manner so as to impart a compressive stress on the substrate.

Abstract translation: 用于互补金属氧化物半导体（CMOS）器件的栅极结构（200）包括具有形成在衬底（100）上的第一栅极电介质层（102）的第一栅极堆叠（116）和形成在衬底 第一栅介质层。 第二栅极堆叠（118）包括形成在衬底上的第二栅极电介质层（102）和形成在第二栅极电介质层上的第二金属层（110）。 第一金属层形成为在基板上施加拉伸应力，并且第二金属层以使得在基板上施加压应力的方式形成。

公开(公告)号：GB2494608B

公开(公告)日：2013-09-04

申请号：GB201300789

申请日：2011-06-10

Applicant: IBM

Inventor： CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON R ,  JOHNSON JEFFREY B ,  LI JINGHONG ,  PARK DAE-GYU ,  ZHU ZHENGMAO

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66

Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack located on an upper surface of a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. The structure further includes embedded stressor elements located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes, from bottom to top, a first layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, a second layer of a second epitaxy doped semiconductor material located atop the first layer, and a delta monolayer of dopant located on an upper surface of the second layer. The structure further includes a metal semiconductor alloy contact located directly on an upper surface of the delta monolayer.

公开(公告)号：DE102012217336A1

公开(公告)日：2013-06-27

申请号：DE102012217336

申请日：2012-09-25

Applicant: IBM

Inventor： CHAN KEVIN K ,  D EMIC CHRISTOPHER ,  KIM YOUNG-HEE ,  PARK DAE-GYU ,  YAU JENG-BANG

IPC: H01L21/283 ,  H01L21/336 ,  H01L21/76 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/49

Abstract: Ein Verfahren zum Ersetzen von Halbleitermaterial durch Metall, Ersatzmetall-Gate-Feldeffekttransistoren (RMGFETs) und Ersatzmetallkontakte (RMCs) und Chips mit integrierten Schaltungen (ICs), welche die FETs und/oder RMCs umfassen. Eine strukturierte Halbleiterschicht, z.B. Silicium, wird auf einer Dielektrikumsschicht, z.B. eines geschichteten Gate-Dielektrikums, gebildet. Eine Feld-Dielektrikumsschicht füllt den Raum zwischen Formen in der strukturierten Halbleiterschicht. Auf die Formen wird Metall aufgebracht. Der Wafer wird getempert, um Halbleiter in jeder Form durch Metall zu ersetzen, um Metall-FET-Gate-Zonen oder Metallkontakte zu bilden.

公开(公告)号：DE102012217336B4

公开(公告)日：2014-02-13

申请号：DE102012217336

申请日：2012-09-25

Applicant: IBM

Inventor： CHAN KEVIN K ,  D EMIC CHRISTOPHER ,  KIM YOUNG-HEE ,  PARK DAE-GYU ,  YAU JENG-BANG

IPC: H01L21/283 ,  H01L21/336 ,  H01L21/76 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/49

Abstract: Verfahren (100) zum Ersetzen von Halbleitermaterial durch Metall, wobei das Verfahren (100) Folgendes aufweist: Bilden einer strukturierten Halbleiterschicht (126) auf einer Dielektrikumsschicht (124); Bilden (106) einer Feld-Dielektrikumsschicht (144; 134, 136, 138) welche den Raum zwischen Formen auf der strukturierten Halbleiterschicht (126) füllt; Aufbringen (110) von Metall (170) auf die Formen (142); und Tempern (112) des Wafers (120), wobei das aufgebrachte Metall (170) in jeder der Formen (142) den Halbleiter ersetzt, wobei es sich bei den Formen um Silicium-Platzhalter und bei dem Metall (170) um Aluminium handelt, und wobei das Aufbringen (110) von Aluminium (170) das Strukturieren einer aufgebrachten Aluminiumschicht (170) in einem Aluminium-Abhebeverfahren aufweist; und das Tempern (112) des Wafers (120) ein Kurzzeittempern für zwei Stunden bei vierhundert Grad Celsius umfasst.

公开(公告)号：GB2492524A

公开(公告)日：2013-01-02

申请号：GB201220031

申请日：2011-04-08

Applicant: IBM

Inventor： CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON ,  LI JINGHONG ,  NEWBURY JOSEPH ,  ONTALUS VIOREL ,  PARK DAE-GYU ,  ZHU ZHENGMAO

IPC: H01L29/78 ,  H01L21/8238

Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include an FET gate stack 18 located on an upper surface of a semiconductor substrate 12. The FET gate stack includes source and drain extension regions 28 located within the semiconductor substrate at a footprint of the FET gate stack. A device channel 40 is also present between the source and drain extension regions and beneath the gate stack. The structure further includes embedded stressor elements 34 located on opposite sides of the FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes a lower layer of a first epitaxy 36 doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy 38 doped semiconductor material located atop the lower layer. The lower layer of the first epitaxy doped semiconductor material has a lower content of dopant as compared to the upper layer of the second epitaxy doped semiconductor material. The structure further includes a monolayer of dopant located within the upper layer of each of the embedded stressor elements. The monolayer of dopant is in direct contact with an edge of either the source extension region or the drain extension region.

公开(公告)号：DE112011101433T5

公开(公告)日：2013-03-28

申请号：DE112011101433

申请日：2011-04-08

Applicant: IBM

Inventor： CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON R ,  LI JINGHONG ,  NEWBURY JOSEPH S ,  ONTALUS VIOREL ,  PARK DAE-GYU ,  ZHU ZHENGMAO

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8228 ,  H01L27/092

Abstract: Es werden Halbleiterstrukturen mit eingebetteten Stressorelementen offenbart. Die offenbarten Strukturen umfassen einen FET-Gate-Stapel 18, der sich auf einer oberen Oberfläche eines Halbleitersubstrats 12 befindet. Der FET-Gate-Stapel umfasst den Source- und den Drain-Erweiterungsbereich 28, die sich in dem Halbleitersubstrat an einer Auflagefläche des FET-Gate-Stapels befinden. Zwischen dem Source- und dem Drain-Erweiterungsbereich und unterhalb des Gate-Stapels ist außerdem ein Bauelementkanal 40 vorhanden. Die Struktur umfasst weiter eingebettete Stressorelemente 34, die sich auf entgegengesetzten Seiten des FET-Gate-Stapels und in dem Halbleitersubstrat befinden. Jedes der eingebetteten Stressorelemente enthält eine untere Schicht eines ersten dotierten Epitaxie-Halbleitermaterials 36 mit einer Gitterkonstante, die sich von einer Gitterkonstante des Halbleitersubstrats unterscheidet und eine Verspannung in den Bauelementkanal überträgt, und eine obere Schicht eines zweiten dotierten Epitaxie-Halbleitermaterials 38, die sich auf der unteren Schicht befindet. Die untere Schicht des ersten dotierten Epitaxie-Halbleitermaterials weist im Vergleich mit der oberen Schicht des zweiten dotierten Epitaxie-Halbleitermaterials einen geringeren Dotierstoffgehalt auf. Die Struktur umfasst weiter eine Dotierstoff-Monoschicht, die sich in der oberen Schicht jedes der eingebetteten Stressorelemente befindet. Die Dotierstoff-Monoschicht steht mit einem Rand entweder des Source-Erweiterungsbereichs oder des Drain-Erweiterungsbereichs in direktem Kontakt.

公开(公告)号：GB2494608A

公开(公告)日：2013-03-13

申请号：GB201300789

申请日：2011-06-10

Applicant: IBM

Inventor： CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON R ,  JOHNSON JEFFREY B ,  LI JINGHONG ,  PARK DAE-GYU ,  ZHU ZHENGMAO

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66

Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack (18) located on an upper surface of a semiconductor substrate (12). The at least one FET gate stack includes source and drain extension regions (28) located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel (40) is also present between the source and drain extension regions (28) and beneath the at least one gate stack (18). The structure further includes embedded stressor elements (33) located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes, from bottom to top, a first layer of a first epitaxy doped semiconductor material (35) having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, a second layer of a second epitaxy doped semiconductor material (36) located atop the first layer, and a delta monolayer of dopant located on an upper surface of the second layer. The structure further includes a metal semiconductor alloy contact (45) located directly on an upper surface of the delta monolayer (37).