公开(公告)号：JP2000003590A

公开(公告)日：2000-01-07

申请号：JP341899

申请日：1999-01-08

Applicant: IBM

Inventor： BARTH JOHN E ,  DREIBELBIS JEFFREY H ,  KALTER HOWARD L

IPC: G11C11/417 ,  G06F12/00 ,  G11C7/10 ,  G11C11/401 ,  G11C11/407 ,  H01L21/822 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To improve the performance of a buried memory macro device by making added information communicated between a storage device and a logic circuit. SOLUTION: This buried memory macro device comprises a storage device 12 and a logic circuit 10 constituted on a common semiconductor substrate. The storage device and the logic circuit communicate with each other using a handshake procedure through a system data interlock signal 26. During a reading cycle. The storage device informs the logic circuit when data in data output of the storage device effective by utilizing the system data interlock signal during a reading cycle, and the storage device informs the logic circuit whether data have been written well by utilizing the system data interlock signal during a writing cycle. After that, the logic circuit instructs the storage device to reset the system interlock signal to make it possible to start instantly new reading or writing.

公开(公告)号：WO2005072287A3

公开(公告)日：2007-04-05

申请号：PCT/US2005002084

申请日：2005-01-24

Applicant: IBM ,  DREIBELBIS JEFFREY H ,  GORMAN KEVIN W ,  NELMS MICHAEL R

Inventor： DREIBELBIS JEFFREY H ,  GORMAN KEVIN W ,  NELMS MICHAEL R

IPC: G01R31/28 ,  G01R31/317 ,  G11C29/00 ,  G11C29/14 ,  G11C29/16 ,  G11C29/44

CPC classification number: G11C29/14 ,  G01R31/31724 ,  G01R31/3187 ,  G11C29/16 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/72 ,  G11C2029/0401

Abstract: Disclosed is a hybrid built-in self test (BIST ) architecture for embedded memory arrays that segments BIST functionality into remote lower-speed executable instructions and. local higher-speed executable instructions. A standalone BIST logic controller (110) operates at a lower frequency and communicates with a plurality of embedded memory arrays (111-113) using a BIST instruction. set. A block of higher-speed test logic (116) is incorporated into each embedded memory array under test and locally processes BIST instructions received from the standalone BIST logic controller (110) at a higher frequency. The higher-speed test logic includes a multiplier (118) for increasing the frequency of the BIST instructions from the lower frequency to the higher frequency. The standalone BIST logic controller (110) enables a plurality of higher-speed test logic structures in a plurality of embedded memory arrays.

Abstract translation: 公开了一种用于嵌入式存储器阵列的混合内置自检（BIST）架构，将BIST功能分段为远程低速可执行指令。 本地更高速的可执行指令。 独立的BIST逻辑控制器（110）以较低的频率工作，并且使用BIST指令与多个嵌入式存储器阵列（111-113）通信。 组。 高速测试逻辑块（116）被并入被测试的每个嵌入式存储器阵列中，并以更高的频率本地处理从独立BIST逻辑控制器（110）接收的BIST指令。 高速测试逻辑包括用于将BIST指令的频率从较低频率增加到较高频率的乘法器（118）。 独立的BIST逻辑控制器（110）使多个嵌入式存储器阵列中的多个更高速的测试逻辑结构成为可能。

公开(公告)号：DE69921708T2

公开(公告)日：2005-11-03

申请号：DE69921708

申请日：1999-01-14

Applicant: IBM

Inventor： BARTH JOHN E ,  DREIBELBIS JEFFREY H ,  KALTER HOWARD L

IPC: G11C11/417 ,  G06F12/00 ,  G11C7/10 ,  G11C11/401 ,  G11C11/407 ,  H01L21/822 ,  H01L27/04 ,  G11C7/00

Abstract: An embedded memory macro device includes a memory system and a logic circuit constructed on a common semiconductor substrate. The memory system and logic circuit communicate through a handshake procedure via a system data interlock signal. During read cycles the memory system uses the system data interlock signal to tell the logic circuit when data at memory system data outputs is valid. In the preferred embodiment, during write cycles the memory system uses the system data interlock signal to tell the logic circuit when data has been successfully written. The logic circuit needs to wait only until the system data interlock signal permits it to proceed. It then signals the memory system to reset the system data interlock signal and can immediately initiate a new read or write cycle.

公开(公告)号：DE69921708D1

公开(公告)日：2004-12-16

申请号：DE69921708

申请日：1999-01-14

Applicant: IBM

Inventor： BARTH JOHN E ,  DREIBELBIS JEFFREY H ,  KALTER HOWARD L

IPC: G11C11/417 ,  G06F12/00 ,  G11C7/10 ,  G11C11/401 ,  G11C11/407 ,  H01L21/822 ,  H01L27/04 ,  G11C7/00

Abstract: An embedded memory macro device includes a memory system and a logic circuit constructed on a common semiconductor substrate. The memory system and logic circuit communicate through a handshake procedure via a system data interlock signal. During read cycles the memory system uses the system data interlock signal to tell the logic circuit when data at memory system data outputs is valid. In the preferred embodiment, during write cycles the memory system uses the system data interlock signal to tell the logic circuit when data has been successfully written. The logic circuit needs to wait only until the system data interlock signal permits it to proceed. It then signals the memory system to reset the system data interlock signal and can immediately initiate a new read or write cycle.

公开(公告)号：MY123248A

公开(公告)日：2006-05-31

申请号：MYPI9904527

申请日：1999-10-20

Applicant: IBM

Inventor： BARTH JOHN E JR ,  BERTIN CLAUDE L ,  DREIBELBIS JEFFREY H ,  ELLIS WAYNE F ,  HOWELL WAYNE J ,  HEDBERG ERIK L ,  KALTER HOWARD LEO ,  TONTI WILLIAM R ,  WHEATER DONALD L

IPC: G11C29/00 ,  H01L21/66 ,  G01R31/28 ,  G01R31/319

Abstract: WAFER TEST AND BURN-IN IS ACCOMPLISHED WITH STATE MACHINE OR PROGRAMMABLE TEST ENGINES (29) LOCATED ON THE WAFER (26) BEING TESTED. EACH TEST ENGINE REQUIRE LESS THAN 10 CONNECTIONS AND EACH TEST ENGINE CAN BE CONNECTED TO A PLURALITY OF CHIPS (28-28", 28A-28E), SUCH AS A ROW OR A COLUMN OF CHIPS ON THE WAFER. THUS, THE NUMBER OF PADS (1-8) OF THE WAFER THAT MUST BE CONNECTED FOR TEST IS SUBSTANTIALLY REDUCED WHILE A LARGE DEGREE OF PARALLEL TESTING IS STILL PROVIDED. THE TEST ENGINES ALSO PERMIT ON-WAFER ALLOCATION OF REDUNDANCY IN PARALLEL SO THAT FAILING CHIPS CAN BE REPAIRED AFTER BURN-IN COMPLETE. IN ADDITION, THE PROGRAMMABLE TEST ENGINES CAN HAVE THEIR CODE ALTERED SO TEST PROGRAMS CAN BE MODIFIED TO ACCOUNT FOR NEW INFORMATION AFTER THE WAFER HAS BEEN FABRICATED. THE TEST ENGINES ARE USED DURING BURN-IN TO PROVIDE HIGH FREQUENCY WRITE SIGNALS TO DRAM ARRAYS THAT PROVIDE A HIGHER EFFECTIVE VOLTAGE TO THE ARRAYS, LOWERING THE TIME REQUIRED FOR BURN-IN. CONNECTIONS TO THE WAFER AND BETWEEN TEST ENGINES AND CHIPS ARE PROVIDED ALONG A MEMBERANE (20-20') ATTACHED TO THE WAFER. MEMBRANE CONNECTORS (31-31") CAN BE FORMED OR OPENED AFTER THE MEMBRANE IS CONNECTED TO THE WAFER SO SHORTED CHIPS CAN BE DISCONNECTED.PREFERABLY THE MEMBRANE REMAINS ON THE WAFER AFTER TEST, BURN-IN AND DICING TO PROVIDE A CHIP SCALE PACKAGE. THUS, THE VERY HIGH COST OF TCE MATCHED MATERIALS, SUCH AS GALSS CERAMIC CONTATCTORS, FOR WAFER BURN-IN IS AVOIDED WHILE PROVIDING BENEFIT BEYOND TEST AND BURN-IN FOR PACKAGING. (FIG. 2)

公开(公告)号：CA1268519A

公开(公告)日：1990-05-01

申请号：CA546779

申请日：1987-09-14

Applicant: IBM

Inventor： DREIBELBIS JEFFREY H ,  FLAKER ROY C ,  HEDBERG ERIK L

IPC: G05F3/24 ,  G05F1/46 ,  G11C5/14 ,  G11C11/407 ,  H02J3/04 ,  H02M1/00 ,  H02M1/10 ,  H03K19/00

Abstract: Power Supply Adapter Systems A power supply adapter system is provided which includes a voltage supply source terminal, an output terminal, first and second switches, the first switch being disposed between the voltage supply source terminal and the output terminal, voltage conversion means serially connected with the second switch and disposed between the voltage supply source terminal and a point of reference potential and having an output coupled to the output terminal, and means for detecting first and second ranges of voltages at the power supply source terminal and for producing first and second control voltages, respectively, to control the first and second switches. BU9-86-016