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    VARIABLE FLOW COMPUTER COOLING SYSTEM FOR A DATA CENTER AND METHOD OF OPERATION
    1.
    发明申请
    VARIABLE FLOW COMPUTER COOLING SYSTEM FOR A DATA CENTER AND METHOD OF OPERATION 审中-公开
    用于数据中心的可变流量计算机冷却系统和操作方法

    公开(公告)号：WO2009107015A2

    公开(公告)日：2009-09-03

    申请号：PCT/IB2009050477

    申请日：2009-02-05

    Applicant: IBM ,  BRUNSCHWILER THOMAS J ,  LINDERMAN RYAN ,  MICHEL BRUNO ,  RUETSCHE ERICH M

    Inventor： BRUNSCHWILER THOMAS J ,  LINDERMAN RYAN ,  MICHEL BRUNO ,  RUETSCHE ERICH M

    IPC: G06F1/20

    CPC classification number: G06F1/20 ,  G06F2200/201 ,  H05K7/20772 ,  Y10S165/908

    Abstract: Disclosed herein is a data center having a plurality of liquid cooled computer systems. The computer systems each include a processor coupled with a cold plate that allows direct liquid cooling of the processor. The cold plate is further arranged to provide adapted flow of coolant to different portions of the processor whereby higher temperature regions receive a larger flow rate of coolant. The flow is variably adjusted to reflect different levels of activity. By maximizing the coolant temperature exiting the computer systems, the system may utilize the free cooling temperature of the ambient air and eliminate the need for a chiller. A data center is further provided that is coupled with a district heating system and heat is extracted from the computer systems is used to offset carbon emissions and reduce the total cost of ownership of the data center.

    Abstract translation: 这里公开了具有多个液冷计算机系统的数据中心。 计算机系统各自包括与冷板相连的处理器，其允许直接液体冷却处理器。 冷板进一步布置成向处理器的不同部分提供适当的冷却流，从而较高的温度区域接收较大的冷却剂流速。 流量被可变地调整以反映不同的活动水平。 通过使离开计算机系统的冷却剂温度最大化，系统可以利用环境空气的自由冷却温度并且消除对冷却器的需要。 还提供了一个与区域供热系统相结合的数据中心，从计算机系统提取的热量用于抵消碳排放，降低数据中心的总体拥有成本。

    Manufacturing an semiconductor chip underfill using air vent
    3.
    发明专利
    Manufacturing an semiconductor chip underfill using air vent 未知

    公开(公告)号：GB2504343A

    公开(公告)日：2014-01-29

    申请号：GB201213365

    申请日：2012-07-27

    Applicant: IBM

    Inventor： BRUNSCHWILER THOMAS J ,  GOICOCHEA JAVIER V ,  OGGIONI STEFANO ,  SCHLOTTIG GERD

    IPC: H01L21/56

    Abstract: A method for manufacturing an underfill in a semiconductor chip stack having a cavity 4 between a first surface (2, figure 1) and a second surface (3). The cavity has multiple access 109 and vent 110 holes in at least one of the said surfaces. Viscous filling material (13) is applied through the access hole into the cavity thereby squeezing air or gas through the vent holes. The filler material may comprise of a carrier fluid 16 and filler particles 17, and be applied to the access holes by way of a dispenser tube 14. The filler material occupies the space within the cavity such that it surrounds solder balls 7. Once the filler material fills the cavity between a particular access hole and vent hole the filler material may instead be inserted through said vent hole. The vent holes may also comprise a filter element which restricts the filler particles 17 from exiting the cavity.

    Optimized semiconductor packaging in a three-dimensional stack
    4.
    发明专利
    Optimized semiconductor packaging in a three-dimensional stack 未知

    公开(公告)号：GB2498892A

    公开(公告)日：2013-07-31

    申请号：GB201308320

    申请日：2011-10-21

    Applicant: IBM

    Inventor： HUBER ANDREAS ,  HARRER HUBERT ,  NIGGEMEIER TIM ,  SUPPER JOCHEN ,  MICHEL BRUNO ,  BRUNSCHWILER THOMAS J ,  PAREDES STEPHAN ,  BAROWSKI HARRY

    IPC: H01L25/065 ,  H01L25/10

    Abstract: A mechanism is provided for optimizing semiconductor packing in a three-dimensional (3D) very-large-scale integration (VLSI) device. The 3D VLSI device comprises a processor layer coupled, via a first set of coupling devices, to at least one signaling and input/output (I/O) layer. The 3D VLSI device further comprises a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the 3D VLSI device the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the three-dimensional VLSI device, and the at least one signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

    Integriertes Schaltungsmodul mit elektrochemischer Leistungsversorgung
    5.
    发明专利
    Integriertes Schaltungsmodul mit elektrochemischer Leistungsversorgung 未知

    公开(公告)号：DE112011102577T5

    公开(公告)日：2013-05-08

    申请号：DE112011102577

    申请日：2011-08-04

    Applicant: IBM

    Inventor： MICHEL BRUNO ,  RUCH PATRICK ,  BRUNSCHWILER THOMAS J

    IPC: H01L23/58

    Abstract: Die Erfindung bezieht sich insbesondere auf ein integriertes Schaltungsmodul (10c). Das Modul weist eine Schichtstruktur auf, bei der ICs und Elektroden (17) in elektrischer Verbindung mit einer Schicht (16) der Schichtstruktur angeordnet sind. Das Modul weist des Weiteren einen oder mehrere Flüssigkeitskreislaufabschnitte (19) auf, die jeweils dazu bestimmt sind, eine jeweilige Elektrolytlösung (oder zwei verschiedene Lösungen, siehe den unten beschriebenen Doppelstrom-Redoxmodus) aufzunehmen. Jede verwendete Lösung weist lösliche elektroaktive Spezies auf. Ein Flüssigkeitsabschnitt ist dazu konzipiert, eine Elektrolytlösung aufzunehmen und ihr zu ermöglichen, mit entsprechenden Elektroden in Kontakt zu treten, um die ICs im Betrieb mit Leistung zu versorgen. Da Elektroden in das Modul integriert sind, kann elektrische Leistung in die Nähe der ICs geführt werden, wodurch der Wirkungsgrad der Leistungsversorgung erhöht wird. Da eine Flüssigkeit in-situ verwendet wird, kann schließlich eine geeignete Wärmeableitung in Betracht gezogen werden, wobei darauf hingewiesen wird, dass eine elektrische Leistungsversorgung und eine Wärmeableitung einander entsprechen.

    Double-face heat removal of vertically integrated chip-stacks utilizing combined symmetric silicon carrier fluid cavity and micro-channel cold plate
    8.
    发明专利
    Double-face heat removal of vertically integrated chip-stacks utilizing combined symmetric silicon carrier fluid cavity and micro-channel cold plate 未知

    公开(公告)号：GB2491519A

    公开(公告)日：2012-12-05

    申请号：GB201215987

    申请日：2011-01-20

    Applicant: IBM

    Inventor： ANDRY PAUL S ,  BRUNSCHWILER THOMAS J ,  COLGAN EVAN ,  MAGERLEIN JOHN H

    IPC: H01L23/14 ,  H01L23/367 ,  H01L23/473 ,  H01L23/498 ,  H01L25/065 ,  H05K7/20

    Abstract: A plurality of heat-dissipating electronic chips are arranged in a vertical chip stack. The electronic chips have electronic components thereon. A cold plate is secured to a back side of the chip stack. A silicon earner sandwich, defining a fluid cavity, is secured to a front side of the chip stack. An inlet manifold is configured to supply cooling fluid to the cold plate and the fluid cavity of the silicon carrier sandwich. An outlet manifold is configured to receive the cooling fluid from the cold plate and the fluid cavity of the silicon carrier sandwich. The cold plate, the silicon earner sandwich, the inlet manifold, and the outlet manifold are configured and dimensioned to electrically isolate the cooling fluid from the electronic components. A method of operating an electronic apparatus and a method of manufacturing an electronic apparatus are also disclosed. Single-sided heat removal with double-sided electrical input-output and double-sided heat removal with double-sided electrical input-output are also disclosed.

    Flip-chip electronic device with carrier having heat dissipation elements free of solder mask
    9.
    发明专利
    Flip-chip electronic device with carrier having heat dissipation elements free of solder mask 未知

    公开(公告)号：GB2520952A

    公开(公告)日：2015-06-10

    申请号：GB201321370

    申请日：2013-12-04

    Applicant: IBM

    Inventor： BRUNSCHWILER THOMAS J ,  SCHLOTTIG GERD ,  OGGIONI STEFANO

    IPC: H01L23/36 ,  H01L23/488

    Abstract: An electronic device 200 of flip-chip type comprises at least one chip carrier 110 having a carrier surface 135, the carrier comprising one or more contact elements 140s,140p of electrically conductive material on the carrier surface, at least one integrated circuit chip 105 having a chip surface 120, the chip comprising one or more terminals 125s,125p of electrically conductive material on the chip surface each one facing a corresponding contact element, solder material 150 soldering each terminal to the corresponding contact element, and restrain means 210s,210p around the contact elements for restraining the solder material during a soldering of the terminals to the contact elements, wherein the carrier comprises one or more heat dissipation elements 205s,205p of thermally conductive material on the carrier surface facing the chip surface displaced from the terminals, the dissipation elements being free of any solder mask. The restrain means 210s,210p may have a surface phobic to solder material.

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