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    METHOD, APPARATUS, AND SYSTEM FOR SOURCE CODING WITH ITERATIVE SIDE INFORMATION GENERATION AND DECODING PROCESS
    3.
    发明申请
    METHOD, APPARATUS, AND SYSTEM FOR SOURCE CODING WITH ITERATIVE SIDE INFORMATION GENERATION AND DECODING PROCESS 审中-公开
    具有迭代信息生成和解码过程的源代码的方法，装置和系统

    公开(公告)号：WO2008084019A2

    公开(公告)日：2008-07-17

    申请号：PCT/EP2008050077

    申请日：2008-01-07

    Applicant: IBM ,  IBM UK ,  HE DAKE ,  JAGMOHAN ASHISH ,  LU LIGANG ,  SHEININ VADIM

    Inventor： HE DAKE ,  JAGMOHAN ASHISH ,  LU LIGANG ,  SHEININ VADIM

    IPC: H04N7/26

    CPC classification number: H04N19/192 ,  H04N19/44 ,  H04N19/46

    Abstract: A method and apparatus for decompressing data in a data-compression system with decoder-only side information is provided. In one aspect, the method comprises generating side information using a source reconstruction and decoding using the generated side information to generate a new source reconstruction. The method further includes iterating the steps of generating and decoding, the generating step using at least the new source reconstruction output by the previous decoding step, and the decoding step using the side information output by the previous generating step. The method may stop the iteration when one or more predetermined criteria are met.

    Abstract translation: 提供了一种用于仅解码侧信息在数据压缩系统中解压缩数据的方法和装置。 一方面，该方法包括使用所生成的侧面信息使用源重构和解码来生成边信息以生成新的源重构。 该方法还包括：使用至少由先前的解码步骤进行的新的源重构输出，生成和解码的步骤，以及使用由前一生成步骤输出的侧信息的解码步骤。 当满足一个或多个预定标准时，该方法可以停止迭代。

    System, method, and computer program for probabilistic multilayer error correction of nand flash memory
    4.
    发明专利
    System, method, and computer program for probabilistic multilayer error correction of nand flash memory 有权
    NAND FLASH存储器的概念多层错误校正的系统，方法和计算机程序

    公开(公告)号：JP2012118979A

    公开(公告)日：2012-06-21

    申请号：JP2011256126

    申请日：2011-11-24

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： JAGMOHAN ASHISH ,  FRANCESCHINI MICHELE MARTINO ,  LUIS A LASTRAS-MONTANO ,  MAYANK SHARMA

    IPC: G06F12/16 ,  G06F11/10 ,  H03M13/29

    CPC classification number: G06F11/1012 ,  H03M13/2906 ,  H03M13/3715 ,  H03M13/3738

    Abstract: PROBLEM TO BE SOLVED: To provide a system, a method, and a computer program for retrieving data from a memory.SOLUTION: Disclosed is error correction of a NAND flash memory including a system for retrieving data from a memory. This system includes a decoder which communicates with the memory. The decoder is operative to implement a method including receiving a code word stored on a page of the memory, and the code word includes data and a check symbol of a first layer generated in accordance with the data. The method further includes determining that the code word includes an error which cannot be corrected using the check symbol of the first layer, and receives a check symbol of a second layer accordingly. The check symbol of the second layer is generated in accordance with the contents of other pages in the memory written before the page including the code word in response to reception of the data. The code word is corrected in accordance with the check symbol of the second layer. The corrected code word is output.

    Abstract translation: 要解决的问题：提供一种用于从存储器检索数据的系统，方法和计算机程序。 解决方案：公开了包括用于从存储器检索数据的系统的NAND闪存的错误校正。 该系统包括与存储器通信的解码器。 解码器用于实现包括接收存储在存储器的页面上的码字的方法，并且码字包括根据数据生成的数据和第一层的校验符号。 该方法还包括确定码字包括使用第一层的检查符号不能校正的错误，并且相应地接收第二层的检查符号。 第二层的检查符号根据接收到数据的包含代码字的页面之前写入的存储器中的其他页面的内容生成。 根据第二层的检查符号校正码字。 输出校正后的代码字。 版权所有（C）2012，JPO＆INPIT

    RECLAIMING DISCARDED SOLID STATE DEVICES
    5.
    发明申请
    RECLAIMING DISCARDED SOLID STATE DEVICES 审中-公开
    重新抛弃固定状态装置

    公开(公告)号：WO2013122691A3

    公开(公告)日：2015-06-11

    申请号：PCT/US2013020470

    申请日：2013-01-07

    Applicant: IBM

    Inventor： FRANCESCHINI MICHELE M ,  JAGMOHAN ASHISH ,  LASTRAS-MONTANO LUIS A ,  SHARMA MAYANK

    IPC: G11C29/00

    CPC classification number: G11C29/56008 ,  G06F11/2289 ,  G06F11/3409 ,  G11C16/349

    Abstract: Discarded memory devices unfit for an original purpose can be reclaimed for reuse for another purpose. The discarded memory devices are tested and evaluated to determine the level of performance degradation therein. A set of an alternate usage and an information encoding scheme to facilitate a reuse of the tested memory device is identified based on the evaluation of the discarded memory device. A memory chip controller may be configured to facilitate usage of reclaimed memory devices by enabling a plurality of encoding schemes therein. Further, a memory device can be configured to facilitate diagnosis of the functionality, and to facilitate usage as a discarded memory unit. Waste due to discarded memory devices can be thereby reduced.

    Abstract translation: 废弃的不适合原始目的的存储设备可以回收再利用用于另一目的。 对废弃的存储器件进行测试和评估，以确定其中性能下降的程度。 基于对废弃的存储器件的评估来识别一组替代使用和信息编码方案，以便于重新使用被测试的存储器件。 存储器芯片控制器可以被配置为通过使能其中的多个编码方案来促进再生存储器件的使用。 此外，存储器装置可以被配置为便于诊断功能，并且便于作为丢弃的存储器单元的使用。 因此可以减少因废弃的存储器件造成的浪费。

    VARIABILITY AWARE WEAR LEVELING
    6.
    发明申请
    VARIABILITY AWARE WEAR LEVELING 审中-公开
    可变性知识磨损水平

    公开(公告)号：WO2013191977A3

    公开(公告)日：2014-02-20

    申请号：PCT/US2013045354

    申请日：2013-06-12

    Applicant: IBM

    Inventor： FRANCESCHINI MICHELE ,  JAGMOHAN ASHISH ,  QURESHI MOINUDDIN KHALIL AHM ,  LASTRAS-MONTANO LUIS A

    IPC: G06F12/02

    CPC classification number: G06F12/0246 ,  G06F12/0292 ,  G06F2212/7201 ,  G06F2212/7211

    Abstract: Techniques are presented that include determining, for data to be written to a nonvolatile memory, a location in the nonvolatile memory to which the data should be written based at least on one or more wear metrics corresponding to the location. The one or more wear metrics are based on measurements of the location. The measurements estimate physical wear of the location. The techniques further include writing the data to the determined location in the nonvolatile memory. The techniques may be performed by methods, apparatus (e.g., a memory controller), and computer program products.

    Abstract translation: 提出了技术，包括至少基于对应于该位置的一个或多个磨损度量，确定要写入非易失性存储器的数据的非易失性存储器中应该写入数据的位置。 一个或多个磨损指标基于位置的测量。 测量值估计位置的物理磨损。 这些技术还包括将数据写入非易失性存储器中的确定位置。 这些技术可以通过方法，装置（例如，存储器控制器）和计算机程序产品来执行。

    Variability aware wear leveling
    7.
    发明专利
    Variability aware wear leveling 未知

    公开(公告)号：GB2516575A

    公开(公告)日：2015-01-28

    申请号：GB201419159

    申请日：2013-06-12

    Applicant: IBM

    Inventor： FRANCESCHINI MICHELE MARTINO ,  QURESHI MOINUDDIN KHALIL AHM ,  JAGMOHAN ASHISH ,  LASTRAS-MONTANO LUIS

    IPC: G06F12/02 ,  G06F12/16

    Abstract: Techniques are presented that include determining, for data to be written to a nonvolatile memory, a location in the nonvolatile memory to which the data should be written based at least on one or more wear metrics corresponding to the location. The one or more wear metrics are based on measurements of the location. The measurements estimate physical wear of the location. The techniques further include writing the data to the determined location in the nonvolatile memory. The techniques may be performed by methods, apparatus (e.g., a memory controller), and computer program products.

    Verfahren und Vorrichtung zur sicheren Verteilung und Speicherung von Daten unter Verwendung von N Kanälen
    8.
    发明专利
    Verfahren und Vorrichtung zur sicheren Verteilung und Speicherung von Daten unter Verwendung von N Kanälen 未知

    公开(公告)号：DE112010005315T5

    公开(公告)日：2012-12-13

    申请号：DE112010005315

    申请日：2010-11-10

    Applicant: IBM

    Inventor： JAGMOHAN ASHISH ,  LIGANG LU ,  HE DAKE

    IPC: H04K1/10

    Abstract: Verfahren und eine Vorrichtung zur sicheren Verteilung und Speicherung von Daten unter Verwendung von N Kanälen werden bereitgestellt. Eine Folge von Eingabedaten, X, wird unter Verwendung einer Vielzahl, N, von Kanälen verteilt. In einer Ausführungsform wird die Folge der Eingabedaten, X, in N Teilfolgen aufgeteilt; und die N Teilfolgen werden mittels eines Satzes von Slepian-Wolf-Codes mit N getrennten Codierern und einem gemeinsamen Decodierer in N Bitströme codiert. Die Slepian-Wolf-Codes können so ausgewählt werden, dass sichergestellt ist, dass eine Rechenkomplexität, um einen Teil der Eingabedatenfolge zu erhalten, in Bezug auf eine Länge der Eingabedatenfolge exponentiell zunimmt, sofern nicht alle der N Bitströme preisgegeben werden. In einer anderen Ausführungsform wird die Folge der Eingabedaten, X, mittels eines verlustfreien Datenkomprimierungsverfahrens komprimiert; und die komprimierte Eingabedatenfolge wird in N Teilfolgen aufgeteilt, die verteilt werden.

    Solid-state storage management
    9.
    发明专利
    Solid-state storage management 未知

    公开(公告)号：GB2511669A

    公开(公告)日：2014-09-10

    申请号：GB201409447

    申请日：2012-11-27

    Applicant: IBM

    Inventor： FRANCESCHINI MICHELE MARTINO ,  JAGMOHAN ASHISH

    IPC: G06F3/06 ,  G06F12/02

    Abstract: Solid-state storage management for a system that includes a main board and a solid-state storage board separate from the main board is provided. The sold-state storage board includes a solid-state memory device and solid-state storage devices. The system is configured to perform a method that includes a correspondence being established, by a software module located on the main board, between a first logical address and a first physical address on the solid-state storage devices. The correspondence between the first logical address and the first physical address is stored in a location on the solid-state memory device. The method also includes translating the first logical address into the first physical address. The translating is performed by an address translator module located on the solid-state storage board and is based on the previously established correspondence between the first logical address and the first physical address.

    Absichern der Inhalte einer Speichereinheit
    10.
    发明专利
    Absichern der Inhalte einer Speichereinheit 未知

    公开(公告)号：DE112014000311B4

    公开(公告)日：2021-10-07

    申请号：DE112014000311

    申请日：2014-01-30

    Applicant: IBM

    Inventor： FRANCESCHINI MICHELE M ,  HUNTER HILLERY C ,  JAGMOHAN ASHISH ,  KILMER CHARLES A ,  KIM KYUHYOUN ,  LASTRAS-MONTANO LUIS A ,  MAULE WARREN E

    IPC: G06F12/14 ,  G11B7/26

    Abstract: Dynamische Direktzugriffsspeicher- (DRAM-) Einheit (100; 200), aufweisend:ein Matrixfeld (105; 205) auf der DRAM-Einheit zum Speichern von Daten, wobei das Matrixfeld zwei oder mehr Zeilen (110) enthält, wobei jede Zeile zwei oder mehr Speicherzellen aufweist;einen Zeilenversionsspeicher auf der DRAM-Einheit für jede Zeile des Arrays, um einen Zeilenversionswert (112; 212) zu speichern; einen Gruppenversionsdatenspeicher (101; 201) auf der DRAM-Einheit zum Speichern eines Gruppenversionswerts (102; 202);und einen Sicherheitscontroller (220) in der DRAM-Einheit, der konfiguriert ist, auf den Empfang einer Löschanforderung zu antworten, indem der Lesezugriff für alle Zeilen des Matrixfelds der DRAM-Einheit gesperrt wird und der Gruppenversionswert in einen neuen Gruppenversionswert geändert wird, wobei es nicht zulässig ist, einen Gruppenversionswert festzulegen, der im Gruppenversionsdatenspeicher gespeichert ist.

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